64b99802a6
* move ethernet to mt7988a.dtsi * move switch definition to mt7988a.dtsi * add PHY LEDs Signed-off-by: Daniel Golle <daniel@makrotopia.org>
1144 lines
28 KiB
Plaintext
1144 lines
28 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "mediatek,mt7988";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator@0 {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x0>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x1>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x2>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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enable-method = "psci";
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reg = <0x3>;
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clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cluster0_opp>;
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mediatek,cci = <&cci>;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <850000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <1100000000>;
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opp-microvolt = <850000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <850000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <900000>;
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};
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};
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};
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cci: cci {
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compatible = "mediatek,mt7988-cci",
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"mediatek,mt8183-cci";
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clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
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<&topckgen CLK_TOP_XTAL>;
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clock-names = "cci", "intermediate";
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operating-points-v2 = <&cci_opp>;
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};
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cci_opp: opp_table_cci {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt = <850000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <660000000>;
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opp-microvolt = <850000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <850000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt = <900000>;
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};
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};
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pmu {
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compatible = "arm,cortex-a73-pmu";
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interrupt-parent = <&gic>;
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interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x50000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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phyfw: phy-firmware@f000000 {
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compatible = "mediatek,2p5gphy-fw";
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reg = <0 0x0f000000 0 0x8000>,
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<0 0x0f100000 0 0x20000>,
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<0 0x0f0f0000 0 0x200>;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7988-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7988-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7988-wdt",
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"mediatek,mt6589-wdt",
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"syscon";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7988-apmixedsys";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7988-pinctrl", "syscon";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c10000 0 0x1000>,
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<0 0x11d00000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11e00000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio_base", "iocfg_tr_base",
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"iocfg_br_base", "iocfg_rb_base",
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"iocfg_lb_base", "iocfg_tl_base", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 84>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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mdio0_pins: mdio0-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio0";
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};
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conf {
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groups = "mdc_mdio0";
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drive-strength = <MTK_DRIVE_8mA>;
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};
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};
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i2c0_pins: i2c0-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c0_1";
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};
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};
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i2c1_pins: i2c1-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c1_0";
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};
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};
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i2c1_sfp_pins: i2c1-sfp-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c1_sfp";
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};
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};
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i2c2_pins: i2c2-pins {
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mux {
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function = "i2c";
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groups = "i2c2";
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};
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};
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i2c2_0_pins: i2c2-pins-g0 {
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mux {
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function = "i2c";
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groups = "i2c2_0";
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};
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};
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i2c2_1_pins: i2c2-pins-g1 {
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mux {
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function = "i2c";
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groups = "i2c2_1";
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};
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};
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gbe0_led0_pins: gbe0-led0-pins {
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mux {
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function = "led";
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groups = "gbe0_led0";
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};
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};
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gbe1_led0_pins: gbe1-led0-pins {
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mux {
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function = "led";
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groups = "gbe1_led0";
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};
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};
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gbe2_led0_pins: gbe2-led0-pins {
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mux {
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function = "led";
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groups = "gbe2_led0";
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};
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};
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gbe3_led0_pins: gbe3-led0-pins {
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mux {
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function = "led";
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groups = "gbe3_led0";
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};
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};
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gbe0_led1_pins: gbe0-led1-pins {
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mux {
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function = "led";
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groups = "gbe0_led1";
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};
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};
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gbe1_led1_pins: gbe1-led1-pins {
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mux {
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function = "led";
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groups = "gbe1_led1";
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};
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};
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gbe2_led1_pins: gbe2-led1-pins {
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mux {
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function = "led";
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groups = "gbe2_led1";
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};
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};
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gbe3_led1_pins: gbe3-led1-pins {
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mux {
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function = "led";
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groups = "gbe3_led1";
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};
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};
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i2p5gbe_led0_pins: 2p5gbe-led0-pins {
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mux {
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function = "led";
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groups = "2p5gbe_led0";
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};
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};
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i2p5gbe_led1_pins: 2p5gbe-led1-pins {
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mux {
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function = "led";
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groups = "2p5gbe_led1";
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};
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};
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mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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};
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mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
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mux {
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function = "flash";
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groups = "emmc_51";
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};
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};
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mmc0_pins_sdcard: mmc0-pins-sdcard {
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mux {
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function = "flash";
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groups = "sdcard";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0";
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};
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};
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7988-sgmiisys",
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"mediatek,mt7988-sgmiisys_0",
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"syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7988-sgmiisys",
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"mediatek,mt7988-sgmiisys_1",
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"syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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usxgmiisys0: usxgmiisys@10080000 {
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compatible = "mediatek,mt7988-usxgmiisys",
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"mediatek,mt7988-usxgmiisys_0",
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"syscon";
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reg = <0 0x10080000 0 0x1000>;
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#clock-cells = <1>;
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};
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usxgmiisys1: usxgmiisys@10081000 {
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compatible = "mediatek,mt7988-usxgmiisys",
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"mediatek,mt7988-usxgmiisys_1",
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"syscon";
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reg = <0 0x10081000 0 0x1000>;
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#clock-cells = <1>;
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};
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xfi_pextp0: xfi_pextp@11f20000 {
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compatible = "mediatek,mt7988-xfi_pextp",
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"mediatek,mt7988-xfi_pextp_0",
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"syscon";
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reg = <0 0x11f20000 0 0x10000>;
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#clock-cells = <1>;
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};
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xfi_pextp1: xfi_pextp@11f30000 {
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compatible = "mediatek,mt7988-xfi_pextp",
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"mediatek,mt7988-xfi_pextp_1",
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"syscon";
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reg = <0 0x11f30000 0 0x10000>;
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#clock-cells = <1>;
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};
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xfi_pll: xfi_pll@11f40000 {
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compatible = "mediatek,mt7988-xfi_pll", "syscon";
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reg = <0 0x11f40000 0 0x1000>;
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#clock-cells = <1>;
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};
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mcusys: mcusys@100e0000 {
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compatible = "mediatek,mt7988-mcusys", "syscon";
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reg = <0 0x100e0000 0 0x1000>;
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#clock-cells = <1>;
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};
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uart0: serial@11000000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11000000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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/*
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* 8250-mtk driver don't control "baud" clock since commit
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* e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
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* still need to be passed to the driver to prevent probe fail
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*/
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_52M_UART0_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "disabled";
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};
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i2c0: i2c@11003000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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reg = <0 0x11003000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11004000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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reg = <0 0x11004000 0 0x1000>,
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<0 0x10217100 0 0x80>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11005000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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reg = <0 0x11005000 0 0x1000>,
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<0 0x10217180 0 0x80>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clock-div = <1>;
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clocks = <&infracfg CLK_INFRA_I2C_BCK>,
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<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@11007000 {
|
|
compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
|
|
reg = <0 0x11007000 0 0x100>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg CLK_INFRA_104M_SPI0>,
|
|
<&infracfg CLK_INFRA_66M_SPI0_HCK>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk",
|
|
"spi-hclk";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2: pcie@11280000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7986-pcie",
|
|
"mediatek,mt8192-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11280000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <3>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x20000000 0x00
|
|
0x20000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x20200000 0x00
|
|
0x20200000 0x00 0x07e00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
|
|
phys = <&xphyu3port0 PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc2 0>,
|
|
<0 0 0 2 &pcie_intc2 1>,
|
|
<0 0 0 3 &pcie_intc2 2>,
|
|
<0 0 0 4 &pcie_intc2 3>;
|
|
pcie_intc2: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
pcie3: pcie@11290000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7986-pcie",
|
|
"mediatek,mt8192-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11290000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <2>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x28000000 0x00
|
|
0x28000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x28200000 0x00
|
|
0x28200000 0x00 0x07e00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc3 0>,
|
|
<0 0 0 2 &pcie_intc3 1>,
|
|
<0 0 0 3 &pcie_intc3 2>,
|
|
<0 0 0 4 &pcie_intc3 3>;
|
|
pcie_intc3: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
pcie0: pcie@11300000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7986-pcie",
|
|
"mediatek,mt8192-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11300000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <0>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x30000000 0x00
|
|
0x30000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x30200000 0x00
|
|
0x30200000 0x00 0x07e00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
|
<0 0 0 2 &pcie_intc0 1>,
|
|
<0 0 0 3 &pcie_intc0 2>,
|
|
<0 0 0 4 &pcie_intc0 3>;
|
|
pcie_intc0: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@11310000 {
|
|
compatible = "mediatek,mt7988-pcie",
|
|
"mediatek,mt7986-pcie",
|
|
"mediatek,mt8192-pcie";
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
reg = <0 0x11310000 0 0x2000>;
|
|
reg-names = "pcie-mac";
|
|
linux,pci-domain = <1>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0x00 0x38000000 0x00
|
|
0x38000000 0x00 0x00200000>,
|
|
<0x82000000 0x00 0x38200000 0x00
|
|
0x38200000 0x00 0x07e00000>;
|
|
clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
|
|
<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
|
|
<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
|
|
<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
|
|
clock-names = "pl_250m", "tl_26m", "peri_26m",
|
|
"top_133m";
|
|
status = "disabled";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
|
<0 0 0 2 &pcie_intc1 1>,
|
|
<0 0 0 3 &pcie_intc1 2>,
|
|
<0 0 0 4 &pcie_intc1 3>;
|
|
pcie_intc1: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
|
|
ssusb0: usb@11190000 {
|
|
compatible = "mediatek,mt7988-xhci",
|
|
"mediatek,mtk-xhci";
|
|
reg = <0 0x11190000 0 0x2e00>,
|
|
<0 0x11193e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&xphyu2port0 PHY_TYPE_USB2>,
|
|
<&xphyu3port0 PHY_TYPE_USB3>;
|
|
clocks = <&infracfg CLK_INFRA_USB_SYS>,
|
|
<&infracfg CLK_INFRA_USB_XHCI>,
|
|
<&infracfg CLK_INFRA_USB_REF>,
|
|
<&infracfg CLK_INFRA_66M_USB_HCK>,
|
|
<&infracfg CLK_INFRA_133M_USB_HCK>;
|
|
clock-names = "sys_ck",
|
|
"xhci_ck",
|
|
"ref_ck",
|
|
"mcu_ck",
|
|
"dma_ck";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
mediatek,p0_speed_fixup;
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusb1: usb@11200000 {
|
|
compatible = "mediatek,mt7988-xhci",
|
|
"mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x2e00>,
|
|
<0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&tphyu2port0 PHY_TYPE_USB2>,
|
|
<&tphyu3port0 PHY_TYPE_USB3>;
|
|
clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
|
|
<&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
|
|
<&infracfg CLK_INFRA_USB_CK_P1>,
|
|
<&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
|
|
<&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
|
|
clock-names = "sys_ck",
|
|
"xhci_ck",
|
|
"ref_ck",
|
|
"mcu_ck",
|
|
"dma_ck";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7986-mmc",
|
|
"mediatek,mt7981-mmc";
|
|
reg = <0 0x11230000 0 0x1000>,
|
|
<0 0x11D60000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
|
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
|
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
|
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
|
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
|
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
|
clock-names = "source",
|
|
"hclk",
|
|
"axi_cg",
|
|
"ahb_cg";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tphy: tphy@11c50000 {
|
|
compatible = "mediatek,mt7988",
|
|
"mediatek,generic-tphy-v2";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
tphyu2port0: usb-phy@11c50000 {
|
|
reg = <0 0x11c50000 0 0x700>;
|
|
clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
tphyu3port0: usb-phy@11c50700 {
|
|
reg = <0 0x11c50700 0 0x900>;
|
|
clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
mediatek,usb3-pll-ssc-delta;
|
|
mediatek,usb3-pll-ssc-delta1;
|
|
};
|
|
};
|
|
|
|
topmisc: topmisc@11d10000 {
|
|
compatible = "mediatek,mt7988-topmisc", "syscon",
|
|
"mediatek,mt7988-power-controller";
|
|
reg = <0 0x11d10000 0 0x10000>;
|
|
#clock-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
xphy: xphy@11e10000 {
|
|
compatible = "mediatek,mt7988",
|
|
"mediatek,xsphy";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
xphyu2port0: usb-phy@11e10000 {
|
|
reg = <0 0x11e10000 0 0x400>;
|
|
clocks = <&infracfg CLK_INFRA_USB_UTMI>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
xphyu3port0: usb-phy@11e13000 {
|
|
reg = <0 0x11e13400 0 0x500>;
|
|
clocks = <&infracfg CLK_INFRA_USB_PIPE>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
mediatek,syscon-type = <&topmisc 0x218 0>;
|
|
};
|
|
};
|
|
|
|
efuse: efuse@11f50000 {
|
|
compatible = "mediatek,efuse";
|
|
reg = <0 0x11f50000 0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
lvts_calibration: calib@918 {
|
|
reg = <0x918 0x28>;
|
|
};
|
|
phy_calibration_p0: calib@940 {
|
|
reg = <0x940 0x10>;
|
|
};
|
|
phy_calibration_p1: calib@954 {
|
|
reg = <0x954 0x10>;
|
|
};
|
|
phy_calibration_p2: calib@968 {
|
|
reg = <0x968 0x10>;
|
|
};
|
|
phy_calibration_p3: calib@97c {
|
|
reg = <0x97c 0x10>;
|
|
};
|
|
cpufreq_calibration: calib@278 {
|
|
reg = <0x278 0x1>;
|
|
};
|
|
};
|
|
|
|
ethsys: syscon@15000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "mediatek,mt7988-ethsys", "syscon";
|
|
reg = <0 0x15000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
switch: switch@15020000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "mediatek,mt7988-switch";
|
|
reg = <0 0x15020000 0 0x8000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <ðrst 0>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
label = "lan0";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
label = "lan1";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy1>;
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
label = "lan2";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy2>;
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
label = "lan3";
|
|
phy-mode = "internal";
|
|
phy-handle = <&gsw_phy3>;
|
|
};
|
|
|
|
port@6 {
|
|
reg = <6>;
|
|
ethernet = <&gmac0>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <10000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mediatek,pio = <&pio>;
|
|
|
|
gsw_phy0: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-id03a2.9481";
|
|
reg = <0>;
|
|
phy-mode = "internal";
|
|
nvmem-cells = <&phy_calibration_p0>;
|
|
nvmem-cell-names = "phy-cal-data";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy0_led0: gsw-phy0-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy0_led1: gsw-phy0-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy1: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-id03a2.9481";
|
|
reg = <1>;
|
|
phy-mode = "internal";
|
|
nvmem-cells = <&phy_calibration_p1>;
|
|
nvmem-cell-names = "phy-cal-data";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy1_led0: gsw-phy1-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy1_led1: gsw-phy1-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy2: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-id03a2.9481";
|
|
reg = <2>;
|
|
phy-mode = "internal";
|
|
nvmem-cells = <&phy_calibration_p2>;
|
|
nvmem-cell-names = "phy-cal-data";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy2_led0: gsw-phy2-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy2_led1: gsw-phy2-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
gsw_phy3: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-id03a2.9481";
|
|
reg = <3>;
|
|
phy-mode = "internal";
|
|
nvmem-cells = <&phy_calibration_p3>;
|
|
nvmem-cell-names = "phy-cal-data";
|
|
|
|
leds {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
gsw_phy3_led0: gsw-phy3-led0@0 {
|
|
reg = <0>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
|
|
gsw_phy3_led1: gsw-phy3-led1@1 {
|
|
reg = <1>;
|
|
function = LED_FUNCTION_LAN;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ethwarp: syscon@15031000 {
|
|
compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
|
|
reg = <0 0x15031000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
|
|
ethrst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
ti,reset-bits = <
|
|
0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
|
|
>;
|
|
};
|
|
};
|
|
|
|
eth: ethernet@15100000 {
|
|
compatible = "mediatek,mt7988-eth";
|
|
reg = <0 0x15100000 0 0x80000>,
|
|
<0 0x15400000 0 0x380000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <ðsys CLK_ETHDMA_XGP1_EN>,
|
|
<ðsys CLK_ETHDMA_XGP2_EN>,
|
|
<ðsys CLK_ETHDMA_XGP3_EN>,
|
|
<ðsys CLK_ETHDMA_FE_EN>,
|
|
<ðsys CLK_ETHDMA_GP2_EN>,
|
|
<ðsys CLK_ETHDMA_GP1_EN>,
|
|
<ðsys CLK_ETHDMA_GP3_EN>,
|
|
<ðsys CLK_ETHDMA_ESW_EN>,
|
|
<ðsys CLK_ETHDMA_CRYPT0_EN>,
|
|
<&sgmiisys0 CLK_SGM0_TX_EN>,
|
|
<&sgmiisys0 CLK_SGM0_RX_EN>,
|
|
<&sgmiisys1 CLK_SGM1_TX_EN>,
|
|
<&sgmiisys1 CLK_SGM1_RX_EN>,
|
|
<ðwarp CLK_ETHWARP_WOCPU2_EN>,
|
|
<ðwarp CLK_ETHWARP_WOCPU1_EN>,
|
|
<ðwarp CLK_ETHWARP_WOCPU0_EN>,
|
|
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
|
|
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
|
|
<&topckgen CLK_TOP_SGM_0_SEL>,
|
|
<&topckgen CLK_TOP_SGM_1_SEL>,
|
|
<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
|
|
<&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
|
|
<&topckgen CLK_TOP_ETH_GMII_SEL>,
|
|
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
|
|
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
|
|
<&topckgen CLK_TOP_ETH_SYS_SEL>,
|
|
<&topckgen CLK_TOP_ETH_XGMII_SEL>,
|
|
<&topckgen CLK_TOP_ETH_MII_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_500M_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_WARP_SEL>;
|
|
clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
|
|
"gp3", "esw", "crypto", "sgmii_tx250m",
|
|
"sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
|
|
"ethwarp_wocpu2", "ethwarp_wocpu1",
|
|
"ethwarp_wocpu0", "top_usxgmii0_sel",
|
|
"top_usxgmii1_sel", "top_sgm0_sel",
|
|
"top_sgm1_sel", "top_xfi_phy0_xtal_sel",
|
|
"top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
|
|
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
|
|
"top_eth_sys_sel", "top_eth_xgmii_sel",
|
|
"top_eth_mii_sel", "top_netsys_sel",
|
|
"top_netsys_500m_sel", "top_netsys_pao_2x_sel",
|
|
"top_netsys_sync_250m_sel",
|
|
"top_netsys_ppefb_250m_sel",
|
|
"top_netsys_warp_sel";
|
|
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_GSW_SEL>,
|
|
<&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
|
|
<&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
|
|
<&topckgen CLK_TOP_SGM_0_SEL>,
|
|
<&topckgen CLK_TOP_SGM_1_SEL>;
|
|
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
|
<&topckgen CLK_TOP_NET1PLL_D4>,
|
|
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
|
|
<&topckgen CLK_TOP_NET1PLL_D8_D4>,
|
|
<&apmixedsys CLK_APMIXED_SGMPLL>,
|
|
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
|
mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
|
|
mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
|
|
mediatek,xfi_pll = <&xfi_pll>;
|
|
mediatek,infracfg = <&topmisc>;
|
|
mediatek,toprgu = <&watchdog>;
|
|
#reset-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
gmac0: mac@0 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <0>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <10000>;
|
|
full-duplex;
|
|
pause;
|
|
};
|
|
};
|
|
|
|
gmac1: mac@1 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <1>;
|
|
};
|
|
|
|
gmac2: mac@2 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <2>;
|
|
};
|
|
|
|
mdio_bus: mdio-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/* internal 2.5G PHY */
|
|
int_2p5g_phy: ethernet-phy@15 {
|
|
reg = <15>;
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
phy-mode = "internal";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|