picnoir/glibc
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Add documentation for __riscv_flush_icache

Browse source 
This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.

2018-01-29  Palmer Dabbelt  <palmer@sifive.com>

        * manual/platform.texi: Add RISC-V documenation for
        __riscv_flush_icache.
This commit is contained in:
Palmer Dabbelt 2018-01-29 10:25:23 -08:00
parent 4215e27674
commit ba9e25a62b
No known key found for this signature in database
GPG key ID: EF4CA1502CCBAB41
2 changed files with 21 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
ChangeLog
View file

@ -4,6 +4,8 @@
PREINIT_FUNCTION when defined.
* manual/math.texi: RISC-V supports _Float128 and _Float64x.
* config.h.in: Regenerate.
* manual/platform.texi: Add RISC-V documenation for
__riscv_flush_icache.
2018-01-29 Florian Weimer <fweimer@redhat.com>

19
manual/platform.texi
View file

@ -6,6 +6,7 @@
@menu
* PowerPC:: Facilities Specific to the PowerPC Architecture
* RISC-V:: Facilities Specific to the RISC-V Architecture
@end menu
@node PowerPC
@ -115,3 +116,21 @@ problem-state programs. If the program priority is medium high when the time
interval expires or if an attempt is made to set the priority to medium high
when it is not allowed, the priority is set to medium.
@end deftypefun
@node RISC-V
@appendixsec RISC-V-specific Facilities
Cache management facilities specific to RISC-V systems that implement the Linux
ABI are declared in @file{sys/cachectl.h}.
@deftypefun {void} __riscv_flush_icache(void *@var{start}, void *@var{end}, unsigned long int @var{flags})
@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}
Enforce ordering between stores and instruction cache fetches. The range of
addresses over which ordering is enforced is specified by @var{start} and
@var{end}. The @var{flags} argument controls the extent of this ordering, with
the default behavior (a @var{flags} value of 0) being to enforce the fence on
all threads in the current process. Setting the
@code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
ordering on only the current thread is necessary. All other flag bits are
reserved.
@end deftypefun