329 lines
8.7 KiB
ArmAsm
329 lines
8.7 KiB
ArmAsm
/* Optimized AVX2 implementation of ChaCha20 cipher.
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Copyright (C) 2022 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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/* chacha20-amd64-avx2.S - AVX2 implementation of ChaCha20 cipher
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Copyright (C) 2017-2019 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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This file is part of Libgcrypt.
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Libgcrypt is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as
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published by the Free Software Foundation; either version 2.1 of
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the License, or (at your option) any later version.
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Libgcrypt is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this program; if not, see <https://www.gnu.org/licenses/>.
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*/
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/* Based on D. J. Bernstein reference implementation at
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http://cr.yp.to/chacha.html:
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chacha-regs.c version 20080118
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D. J. Bernstein
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Public domain. */
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#include <sysdep.h>
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#ifdef PIC
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# define rRIP (%rip)
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#else
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# define rRIP
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#endif
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/* register macros */
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#define INPUT %rdi
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#define DST %rsi
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#define SRC %rdx
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#define NBLKS %rcx
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#define ROUND %eax
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/* stack structure */
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#define STACK_VEC_X12 (32)
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#define STACK_VEC_X13 (32 + STACK_VEC_X12)
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#define STACK_TMP (32 + STACK_VEC_X13)
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#define STACK_TMP1 (32 + STACK_TMP)
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#define STACK_MAX (32 + STACK_TMP1)
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/* vector registers */
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#define X0 %ymm0
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#define X1 %ymm1
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#define X2 %ymm2
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#define X3 %ymm3
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#define X4 %ymm4
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#define X5 %ymm5
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#define X6 %ymm6
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#define X7 %ymm7
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#define X8 %ymm8
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#define X9 %ymm9
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#define X10 %ymm10
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#define X11 %ymm11
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#define X12 %ymm12
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#define X13 %ymm13
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#define X14 %ymm14
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#define X15 %ymm15
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#define X0h %xmm0
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#define X1h %xmm1
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#define X2h %xmm2
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#define X3h %xmm3
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#define X4h %xmm4
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#define X5h %xmm5
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#define X6h %xmm6
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#define X7h %xmm7
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#define X8h %xmm8
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#define X9h %xmm9
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#define X10h %xmm10
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#define X11h %xmm11
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#define X12h %xmm12
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#define X13h %xmm13
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#define X14h %xmm14
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#define X15h %xmm15
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/**********************************************************************
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helper macros
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**********************************************************************/
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/* 4x4 32-bit integer matrix transpose */
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#define transpose_4x4(x0,x1,x2,x3,t1,t2) \
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vpunpckhdq x1, x0, t2; \
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vpunpckldq x1, x0, x0; \
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\
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vpunpckldq x3, x2, t1; \
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vpunpckhdq x3, x2, x2; \
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\
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vpunpckhqdq t1, x0, x1; \
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vpunpcklqdq t1, x0, x0; \
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\
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vpunpckhqdq x2, t2, x3; \
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vpunpcklqdq x2, t2, x2;
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/* 2x2 128-bit matrix transpose */
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#define transpose_16byte_2x2(x0,x1,t1) \
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vmovdqa x0, t1; \
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vperm2i128 $0x20, x1, x0, x0; \
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vperm2i128 $0x31, x1, t1, x1;
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/**********************************************************************
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8-way chacha20
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**********************************************************************/
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#define ROTATE2(v1,v2,c,tmp) \
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vpsrld $(32 - (c)), v1, tmp; \
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vpslld $(c), v1, v1; \
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vpaddb tmp, v1, v1; \
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vpsrld $(32 - (c)), v2, tmp; \
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vpslld $(c), v2, v2; \
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vpaddb tmp, v2, v2;
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#define ROTATE_SHUF_2(v1,v2,shuf) \
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vpshufb shuf, v1, v1; \
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vpshufb shuf, v2, v2;
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#define XOR(ds,s) \
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vpxor s, ds, ds;
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#define PLUS(ds,s) \
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vpaddd s, ds, ds;
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#define QUARTERROUND2(a1,b1,c1,d1,a2,b2,c2,d2,ign,tmp1,\
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interleave_op1,interleave_op2,\
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interleave_op3,interleave_op4) \
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vbroadcasti128 .Lshuf_rol16 rRIP, tmp1; \
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interleave_op1; \
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PLUS(a1,b1); PLUS(a2,b2); XOR(d1,a1); XOR(d2,a2); \
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ROTATE_SHUF_2(d1, d2, tmp1); \
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interleave_op2; \
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PLUS(c1,d1); PLUS(c2,d2); XOR(b1,c1); XOR(b2,c2); \
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ROTATE2(b1, b2, 12, tmp1); \
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vbroadcasti128 .Lshuf_rol8 rRIP, tmp1; \
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interleave_op3; \
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PLUS(a1,b1); PLUS(a2,b2); XOR(d1,a1); XOR(d2,a2); \
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ROTATE_SHUF_2(d1, d2, tmp1); \
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interleave_op4; \
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PLUS(c1,d1); PLUS(c2,d2); XOR(b1,c1); XOR(b2,c2); \
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ROTATE2(b1, b2, 7, tmp1);
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.section .text.avx2, "ax", @progbits
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.align 32
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chacha20_data:
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L(shuf_rol16):
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.byte 2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13
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L(shuf_rol8):
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.byte 3,0,1,2,7,4,5,6,11,8,9,10,15,12,13,14
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L(inc_counter):
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.byte 0,1,2,3,4,5,6,7
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L(unsigned_cmp):
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.long 0x80000000
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.hidden __chacha20_avx2_blocks8
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ENTRY (__chacha20_avx2_blocks8)
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/* input:
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* %rdi: input
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* %rsi: dst
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* %rdx: src
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* %rcx: nblks (multiple of 8)
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*/
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vzeroupper;
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pushq %rbp;
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cfi_adjust_cfa_offset(8);
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cfi_rel_offset(rbp, 0)
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movq %rsp, %rbp;
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cfi_def_cfa_register(rbp);
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subq $STACK_MAX, %rsp;
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andq $~31, %rsp;
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L(loop8):
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mov $20, ROUND;
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/* Construct counter vectors X12 and X13 */
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vpmovzxbd L(inc_counter) rRIP, X0;
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vpbroadcastd L(unsigned_cmp) rRIP, X2;
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vpbroadcastd (12 * 4)(INPUT), X12;
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vpbroadcastd (13 * 4)(INPUT), X13;
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vpaddd X0, X12, X12;
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vpxor X2, X0, X0;
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vpxor X2, X12, X1;
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vpcmpgtd X1, X0, X0;
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vpsubd X0, X13, X13;
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vmovdqa X12, (STACK_VEC_X12)(%rsp);
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vmovdqa X13, (STACK_VEC_X13)(%rsp);
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/* Load vectors */
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vpbroadcastd (0 * 4)(INPUT), X0;
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vpbroadcastd (1 * 4)(INPUT), X1;
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vpbroadcastd (2 * 4)(INPUT), X2;
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vpbroadcastd (3 * 4)(INPUT), X3;
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vpbroadcastd (4 * 4)(INPUT), X4;
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vpbroadcastd (5 * 4)(INPUT), X5;
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vpbroadcastd (6 * 4)(INPUT), X6;
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vpbroadcastd (7 * 4)(INPUT), X7;
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vpbroadcastd (8 * 4)(INPUT), X8;
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vpbroadcastd (9 * 4)(INPUT), X9;
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vpbroadcastd (10 * 4)(INPUT), X10;
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vpbroadcastd (11 * 4)(INPUT), X11;
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vpbroadcastd (14 * 4)(INPUT), X14;
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vpbroadcastd (15 * 4)(INPUT), X15;
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vmovdqa X15, (STACK_TMP)(%rsp);
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L(round2):
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QUARTERROUND2(X0, X4, X8, X12, X1, X5, X9, X13, tmp:=,X15,,,,)
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vmovdqa (STACK_TMP)(%rsp), X15;
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vmovdqa X8, (STACK_TMP)(%rsp);
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QUARTERROUND2(X2, X6, X10, X14, X3, X7, X11, X15, tmp:=,X8,,,,)
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QUARTERROUND2(X0, X5, X10, X15, X1, X6, X11, X12, tmp:=,X8,,,,)
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vmovdqa (STACK_TMP)(%rsp), X8;
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vmovdqa X15, (STACK_TMP)(%rsp);
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QUARTERROUND2(X2, X7, X8, X13, X3, X4, X9, X14, tmp:=,X15,,,,)
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sub $2, ROUND;
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jnz L(round2);
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vmovdqa X8, (STACK_TMP1)(%rsp);
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/* tmp := X15 */
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vpbroadcastd (0 * 4)(INPUT), X15;
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PLUS(X0, X15);
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vpbroadcastd (1 * 4)(INPUT), X15;
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PLUS(X1, X15);
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vpbroadcastd (2 * 4)(INPUT), X15;
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PLUS(X2, X15);
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vpbroadcastd (3 * 4)(INPUT), X15;
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PLUS(X3, X15);
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vpbroadcastd (4 * 4)(INPUT), X15;
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PLUS(X4, X15);
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vpbroadcastd (5 * 4)(INPUT), X15;
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PLUS(X5, X15);
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vpbroadcastd (6 * 4)(INPUT), X15;
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PLUS(X6, X15);
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vpbroadcastd (7 * 4)(INPUT), X15;
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PLUS(X7, X15);
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transpose_4x4(X0, X1, X2, X3, X8, X15);
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transpose_4x4(X4, X5, X6, X7, X8, X15);
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vmovdqa (STACK_TMP1)(%rsp), X8;
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transpose_16byte_2x2(X0, X4, X15);
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transpose_16byte_2x2(X1, X5, X15);
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transpose_16byte_2x2(X2, X6, X15);
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transpose_16byte_2x2(X3, X7, X15);
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vmovdqa (STACK_TMP)(%rsp), X15;
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vmovdqu X0, (64 * 0 + 16 * 0)(DST)
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vmovdqu X1, (64 * 1 + 16 * 0)(DST)
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vpbroadcastd (8 * 4)(INPUT), X0;
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PLUS(X8, X0);
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vpbroadcastd (9 * 4)(INPUT), X0;
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PLUS(X9, X0);
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vpbroadcastd (10 * 4)(INPUT), X0;
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PLUS(X10, X0);
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vpbroadcastd (11 * 4)(INPUT), X0;
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PLUS(X11, X0);
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vmovdqa (STACK_VEC_X12)(%rsp), X0;
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PLUS(X12, X0);
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vmovdqa (STACK_VEC_X13)(%rsp), X0;
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PLUS(X13, X0);
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vpbroadcastd (14 * 4)(INPUT), X0;
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PLUS(X14, X0);
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vpbroadcastd (15 * 4)(INPUT), X0;
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PLUS(X15, X0);
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vmovdqu X2, (64 * 2 + 16 * 0)(DST)
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vmovdqu X3, (64 * 3 + 16 * 0)(DST)
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/* Update counter */
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addq $8, (12 * 4)(INPUT);
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transpose_4x4(X8, X9, X10, X11, X0, X1);
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transpose_4x4(X12, X13, X14, X15, X0, X1);
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vmovdqu X4, (64 * 4 + 16 * 0)(DST)
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vmovdqu X5, (64 * 5 + 16 * 0)(DST)
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transpose_16byte_2x2(X8, X12, X0);
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transpose_16byte_2x2(X9, X13, X0);
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transpose_16byte_2x2(X10, X14, X0);
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transpose_16byte_2x2(X11, X15, X0);
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vmovdqu X6, (64 * 6 + 16 * 0)(DST)
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vmovdqu X7, (64 * 7 + 16 * 0)(DST)
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vmovdqu X8, (64 * 0 + 16 * 2)(DST)
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vmovdqu X9, (64 * 1 + 16 * 2)(DST)
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vmovdqu X10, (64 * 2 + 16 * 2)(DST)
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vmovdqu X11, (64 * 3 + 16 * 2)(DST)
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vmovdqu X12, (64 * 4 + 16 * 2)(DST)
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vmovdqu X13, (64 * 5 + 16 * 2)(DST)
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vmovdqu X14, (64 * 6 + 16 * 2)(DST)
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vmovdqu X15, (64 * 7 + 16 * 2)(DST)
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sub $8, NBLKS;
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lea (8 * 64)(DST), DST;
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lea (8 * 64)(SRC), SRC;
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jnz L(loop8);
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vzeroupper;
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/* eax zeroed by round loop. */
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leave;
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cfi_adjust_cfa_offset(-8)
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cfi_def_cfa_register(%rsp);
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ret;
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int3;
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END(__chacha20_avx2_blocks8)
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