120 lines
3.6 KiB
C
120 lines
3.6 KiB
C
/* Initialize CPU feature data. AArch64 version.
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This file is part of the GNU C Library.
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Copyright (C) 2017-2021 Free Software Foundation, Inc.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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<https://www.gnu.org/licenses/>. */
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#include <cpu-features.h>
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#include <sys/auxv.h>
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#include <elf/dl-hwcaps.h>
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#include <sys/prctl.h>
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#define DCZID_DZP_MASK (1 << 4)
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#define DCZID_BS_MASK (0xf)
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/* The maximal set of permitted tags that the MTE random tag generation
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instruction may use. We exclude tag 0 because a) we want to reserve
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that for the libc heap structures and b) because it makes it easier
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to see when pointer have been correctly tagged. */
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#define MTE_ALLOWED_TAGS (0xfffe << PR_MTE_TAG_SHIFT)
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#if HAVE_TUNABLES
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struct cpu_list
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{
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const char *name;
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uint64_t midr;
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};
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static struct cpu_list cpu_list[] = {
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{"falkor", 0x510FC000},
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{"thunderxt88", 0x430F0A10},
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{"thunderx2t99", 0x431F0AF0},
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{"thunderx2t99p1", 0x420F5160},
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{"phecda", 0x680F0000},
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{"ares", 0x411FD0C0},
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{"emag", 0x503F0001},
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{"kunpeng920", 0x481FD010},
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{"generic", 0x0}
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};
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static uint64_t
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get_midr_from_mcpu (const char *mcpu)
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{
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for (int i = 0; i < sizeof (cpu_list) / sizeof (struct cpu_list); i++)
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if (strcmp (mcpu, cpu_list[i].name) == 0)
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return cpu_list[i].midr;
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return UINT64_MAX;
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}
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#endif
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static inline void
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init_cpu_features (struct cpu_features *cpu_features)
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{
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register uint64_t midr = UINT64_MAX;
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#if HAVE_TUNABLES
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/* Get the tunable override. */
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const char *mcpu = TUNABLE_GET (glibc, cpu, name, const char *, NULL);
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if (mcpu != NULL)
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midr = get_midr_from_mcpu (mcpu);
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#endif
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/* If there was no useful tunable override, query the MIDR if the kernel
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allows it. */
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if (midr == UINT64_MAX)
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{
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if (GLRO (dl_hwcap) & HWCAP_CPUID)
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asm volatile ("mrs %0, midr_el1" : "=r"(midr));
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else
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midr = 0;
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}
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cpu_features->midr_el1 = midr;
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/* Check if ZVA is enabled. */
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unsigned dczid;
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asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
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if ((dczid & DCZID_DZP_MASK) == 0)
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cpu_features->zva_size = 4 << (dczid & DCZID_BS_MASK);
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/* Check if BTI is supported. */
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cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI;
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/* Setup memory tagging support if the HW and kernel support it, and if
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the user has requested it. */
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cpu_features->mte_state = 0;
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#ifdef USE_MTAG
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# if HAVE_TUNABLES
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int mte_state = TUNABLE_GET (glibc, mem, tagging, unsigned, 0);
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cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0;
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/* If we lack the MTE feature, disable the tunable, since it will
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otherwise cause instructions that won't run on this CPU to be used. */
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TUNABLE_SET (glibc, mem, tagging, cpu_features->mte_state);
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# endif
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if (cpu_features->mte_state & 2)
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__prctl (PR_SET_TAGGED_ADDR_CTRL,
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(PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
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0, 0, 0);
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else if (cpu_features->mte_state)
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__prctl (PR_SET_TAGGED_ADDR_CTRL,
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(PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC | MTE_ALLOWED_TAGS),
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0, 0, 0);
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#endif
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}
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