8b4f6aeb7a
Change the cache clear instructions for generated PPC64LE code so that it uses an input variable instead of an output variable. With an output variable, it doesn't use the correct address for the dcbst and icbi instructions, possibly causing it to crash.
267 lines
8.1 KiB
C
267 lines
8.1 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and/or associated documentation files (the
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* "Materials"), to deal in the Materials without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Materials, and to
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* permit persons to whom the Materials are furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* unaltered in all copies or substantial portions of the Materials.
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* Any additions, deletions, or changes to the original source files
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* must be clearly indicated in accompanying documentation.
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*
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* If only executable code is distributed, then the accompanying
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* documentation must state that "this software is based in part on the
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* work of the Khronos Group."
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*
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* THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
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*/
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#include "patchentrypoints.h"
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#include <string.h>
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#include <assert.h>
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#include "compiler.h"
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#include "utils_misc.h"
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static void patch_x86_64(char *writeEntry, const char *execEntry,
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int stubSize, void *incrementPtr)
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{
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#if defined(__x86_64__)
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// On an x32 build, pointers are 32 bits, but the code that we generate
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// here uses a 64-bit address. Cast incrementPtr to a 64-bit integer so
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// that it's the right size for either build.
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uint64_t incrementAddr = (uint64_t) ((uintptr_t) incrementPtr);
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const char tmpl[] = {
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0xa1, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12, // movabs 0x123456789abcdef0, %eax
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0x83, 0xc0, 0x01, // add $0x1,%eax
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0xa3, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12, // movabs %eax,0x123456789abcdef0
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0xc3, // ret
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};
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if (stubSize < sizeof(tmpl)) {
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return;
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}
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memcpy(writeEntry, tmpl, sizeof(tmpl));
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memcpy(writeEntry + 1, &incrementAddr, sizeof(incrementAddr));
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memcpy(writeEntry + 13, &incrementAddr, sizeof(incrementAddr));
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#else
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assert(0); // Should not be calling this
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#endif
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}
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static void patch_x86(char *writeEntry, const char *execEntry,
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int stubSize, void *incrementPtr)
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{
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#if defined(__i386__)
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uintptr_t *p;
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char tmpl[] = {
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0xa1, 0x0, 0x0, 0x0, 0x0, // mov 0x0, %eax
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0x83, 0xc0, 0x01, // add $0x1, %eax
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0xa3, 0x0, 0x0, 0x0, 0x0, // mov %eax, 0x0
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0xc3 // ret
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};
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STATIC_ASSERT(sizeof(int) == 0x4);
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if (stubSize < sizeof(tmpl)) {
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return;
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}
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// Patch the address of the incrementPtr variable.
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p = (uintptr_t *)&tmpl[1];
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*p = (uintptr_t) incrementPtr;
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p = (uintptr_t *)&tmpl[9];
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*p = (uintptr_t) incrementPtr;
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memcpy(writeEntry, tmpl, sizeof(tmpl));
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// Jump to an intermediate location
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__asm__(
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"\tjmp 0f\n"
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"\t0:\n"
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);
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#else
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assert(0); // Should not be calling this
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#endif
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}
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static void patch_armv7_thumb(char *writeEntry, const char *execEntry,
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int stubSize, void *incrementPtr)
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{
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#if defined(__arm__)
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// Thumb bytecode
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const uint16_t tmpl[] = {
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0x4802, // ldr r0, 1f
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0x6801, // ldr r1, [r0]
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0xf101, 0x0101, // add r1, r1, #1
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0x6001, // str r1, [r0]
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0x4770, // bx lr
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// 1:
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0x0000, 0x0000,
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};
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static int offsetAddr = sizeof(tmpl) - 4;
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if (stubSize < sizeof(tmpl)) {
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return;
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}
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memcpy(writeEntry, tmpl, sizeof(tmpl));
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*((uint32_t *)(writeEntry + offsetAddr)) = (uint32_t)incrementPtr;
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__builtin___clear_cache((char *) execEntry, (char *) (execEntry + sizeof(tmpl)));
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#else
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assert(0); // Should not be calling this
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#endif
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}
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static void patch_aarch64(char *writeEntry, const char *execEntry,
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int stubSize, void *incrementPtr)
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{
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#if defined(__aarch64__)
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const uint32_t tmpl[] = {
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// ldr x0, 1f
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0x580000a0,
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// ldr x1, [x0]
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0xf9400001,
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// add x1, x1, #1
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0x91000421,
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// str x1, [x0]
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0xf9000001,
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// br x30
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0xd61f03c0,
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// 1:
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0x00000000, 0x00000000,
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};
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static const int offsetAddr = sizeof(tmpl) - 8;
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if (stubSize < sizeof(tmpl)) {
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return;
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}
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memcpy(writeEntry, tmpl, sizeof(tmpl));
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*((uint64_t *)(writeEntry + offsetAddr)) = (uint64_t) incrementPtr;
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__builtin___clear_cache((char *) execEntry, (char *) (execEntry + sizeof(tmpl)));
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#else
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assert(0); // Should not be calling this
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#endif
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}
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static void patch_ppc64le(char *writeEntry, const char *execEntry,
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int stubSize, void *incrementPtr)
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{
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#if defined(__PPC64__)
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const unsigned int tmpl[] = {
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// NOTE!!! NOTE!!! NOTE!!!
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// This representation is correct for both little- and big-endian systems.
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// However, more work needs to be done for big-endian Linux because it
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// adheres to an older, AIX-compatible ABI that uses function descriptors.
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// 1000:
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0x7D2903A6, // mtctr 9
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0xE96C0020, // ld 11, 9000f-1000b(12)
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0xE92B0000, // ld 9, 0(11)
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0x39290001, // addi 9, 9, 1
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0xF92B0000, // std 9, 0(11)
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0x7D2902A6, // mfctr 9
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0x4E800020, // blr
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0x60000000, // nop
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// 9000:
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0, 0
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};
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static const int offsetAddr = sizeof(tmpl) - 8;
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if (stubSize < sizeof(tmpl)) {
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return;
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}
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memcpy(writeEntry, tmpl, sizeof(tmpl));
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memcpy(writeEntry + offsetAddr, &incrementPtr, sizeof(incrementPtr));
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// This sequence is from the PowerISA Version 2.07B book.
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// It may be a bigger hammer than we need, but it works;
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// note that the __builtin___clear_cache intrinsic for
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// PPC does not seem to generate any code:
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__asm__ __volatile__(
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" dcbst 0, %0\n\t"
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" sync\n\t"
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" icbi 0, %0\n\t"
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" isync\n"
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: : "r" (writeEntry)
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);
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#else
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assert(0); // Should not be calling this
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#endif
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}
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GLboolean dummyCheckPatchSupported(int type, int stubSize)
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{
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switch (type) {
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case __GLDISPATCH_STUB_X86_64:
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case __GLDISPATCH_STUB_X86:
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case __GLDISPATCH_STUB_ARMV7_THUMB:
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case __GLDISPATCH_STUB_AARCH64:
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case __GLDISPATCH_STUB_X32:
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case __GLDISPATCH_STUB_PPC64LE:
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return GL_TRUE;
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default:
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return GL_FALSE;
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}
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}
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GLboolean dummyPatchFunction(int type, int stubSize,
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DispatchPatchLookupStubOffset lookupStubOffset,
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const char *name, int *incrementPtr)
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{
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void *writeAddr;
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const void *execAddr;
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if (!dummyCheckPatchSupported(type, stubSize)) {
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return GL_FALSE;
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}
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if (lookupStubOffset(name, &writeAddr, &execAddr)) {
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switch (type) {
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case __GLDISPATCH_STUB_X86_64:
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case __GLDISPATCH_STUB_X32:
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patch_x86_64(writeAddr, execAddr, stubSize, incrementPtr);
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break;
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case __GLDISPATCH_STUB_X86:
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patch_x86(writeAddr, execAddr, stubSize, incrementPtr);
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break;
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case __GLDISPATCH_STUB_ARMV7_THUMB:
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patch_armv7_thumb(writeAddr, execAddr, stubSize, incrementPtr);
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break;
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case __GLDISPATCH_STUB_AARCH64:
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patch_aarch64(writeAddr, execAddr, stubSize, incrementPtr);
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break;
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case __GLDISPATCH_STUB_PPC64LE:
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patch_ppc64le(writeAddr, execAddr, stubSize, incrementPtr);
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break;
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default:
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assert(0);
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}
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}
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return GL_TRUE;
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}
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