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10 Commits
04f6d674f6
...
1eb67cb070
| Author | SHA1 | Date |
|---|---|---|
Daniel Golle
|
1eb67cb070 | |
|
Felix Fietkau
|
b8be20c7e8 | |
|
Daniel Golle
|
64b99802a6 | |
|
Daniel Golle
|
36d0aa9c2d | |
|
Daniel Golle
|
2a5c7bf621 | |
|
Stijn Tintel
|
15acde674c | |
|
Nick Hainke
|
57fda4b743 | |
|
Stefan Kalscheuer
|
801c67b4e0 | |
|
Stefan Kalscheuer
|
b1993f362a | |
|
Stefan Kalscheuer
|
7f257296ec |
|
|
@ -308,6 +308,24 @@ endef
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$(eval $(call KernelPackage,phy-marvell))
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define KernelPackage/phy-marvell-10g
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SUBMENU:=$(NETWORK_DEVICES_MENU)
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TITLE:=Marvell 10 Gigabit Ethernet PHY driver
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KCONFIG:=CONFIG_MARVELL_10G_PHY
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DEPENDS:=+kmod-libphy
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FILES:=$(LINUX_DIR)/drivers/net/phy/marvell10g.ko
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AUTOLOAD:=$(call AutoLoad,18,marvell10g)
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endef
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define KernelPackage/phy-marvell/description
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Supports Marvell 10 Gigabit Ethernet PHYs:
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* 88E2110
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* 88E2111
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* 88x3310
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* 88x3340
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endef
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$(eval $(call KernelPackage,phy-marvell-10g))
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define KernelPackage/phy-realtek
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SUBMENU:=$(NETWORK_DEVICES_MENU)
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@ -1,7 +1,7 @@
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#!/usr/bin/env ucode
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'use strict';
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import { vlist_new, is_equal, wdev_create, wdev_remove } from "/usr/share/hostap/common.uc";
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import { readfile, writefile, basename, glob } from "fs";
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import { readfile, writefile, basename, readlink, glob } from "fs";
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let keep_devices = {};
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let phy = shift(ARGV);
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@ -106,6 +106,9 @@ function add_existing(phy, config)
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if (config[wdev])
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continue;
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if (basename(readlink(`/sys/class/net/${wdev}/phy80211`)) != phy)
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continue;
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if (trim(readfile(`/sys/class/net/${wdev}/operstate`)) == "down")
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config[wdev] = {};
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}
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@ -94,7 +94,7 @@ MAKE_VARS += \
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define Build/Configure
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$(call Build/Configure/Default)
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echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib" >> $(PKG_BUILD_DIR)/config.mk
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echo "BPF_CFLAGS += -I$(BPF_HEADERS_DIR)/tools/lib -fno-stack-protector" >> $(PKG_BUILD_DIR)/config.mk
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endef
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define Build/InstallDev
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include "mt7988a-rfb-spim-nand.dtsi"
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
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@ -29,173 +30,105 @@
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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&gmac0 {
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&int_2p5g_phy>;
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};
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&gmac2 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-connection-type = "usxgmii";
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phy = <&phy8>;
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};
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&mdio_bus {
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "internal";
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phy-connection-type = "internal";
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phy = <&phy15>;
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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gmac2: mac@2 {
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compatible = "mediatek,eth-mac";
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reg = <2>;
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phy-mode = "10gbase-kr";
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phy-connection-type = "10gbase-kr";
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phy = <&phy8>;
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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mdio0: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* external Aquantia AQR113C */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 72 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Aquantia AQR113C */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c45";
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reset-gpios = <&pio 71 1>;
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reset-assert-us = <100000>;
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reset-deassert-us = <221000>;
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};
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/* external Maxlinear GPY211C */
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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/* internal 2.5G PHY */
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phy15: ethernet-phy@15 {
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reg = <15>;
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "internal";
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};
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/* external Maxlinear GPY211C */
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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&int_2p5g_phy {
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pinctrl-names = "i2p5gbe-led";
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pinctrl-0 = <&i2p5gbe_led0_pins>;
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};
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&switch {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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phy-mode = "internal";
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phy-handle = <&gsw_phy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&gsw_phy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&gsw_phy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&gsw_phy3>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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mediatek,pio = <&pio>;
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gsw_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <0>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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nvmem-cells = <&phy_calibration_p0>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <1>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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nvmem-cells = <&phy_calibration_p1>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <2>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe2_led0_pins>;
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nvmem-cells = <&phy_calibration_p2>;
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nvmem-cell-names = "phy-cal-data";
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};
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gsw_phy3: ethernet-phy@3 {
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compatible = "ethernet-phy-id03a2.9481";
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reg = <3>;
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phy-mode = "internal";
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe3_led0_pins>;
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nvmem-cells = <&phy_calibration_p3>;
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nvmem-cell-names = "phy-cal-data";
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};
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};
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};
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&gsw_phy0 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe0_led0_pins>;
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};
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&gsw_phy0_led0 {
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status = "okay";
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color = <LED_COLOR_ID_GREEN>;
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};
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&gsw_phy1 {
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pinctrl-names = "gbe-led";
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pinctrl-0 = <&gbe1_led0_pins>;
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};
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&gsw_phy1_led0 {
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status = "okay";
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||||
color = <LED_COLOR_ID_GREEN>;
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||||
};
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||||
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||||
&gsw_phy2 {
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||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe2_led0_pins>;
|
||||
};
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||||
|
||||
&gsw_phy2_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy3 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe3_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy3_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,12 +4,13 @@
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|||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/reset/ti-syscon.h>
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/reset/ti-syscon.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -144,9 +145,9 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
reg = <0 0x43000000 0 0x50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
|
@ -228,7 +229,7 @@
|
|||
"iocfg_lb_base", "iocfg_tl_base", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 83>;
|
||||
gpio-ranges = <&pio 0 0 84>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -260,47 +261,131 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins-g0 {
|
||||
i2c1_sfp_pins: i2c1-sfp-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c1_sfp";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_0_pins: i2c2-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2_0";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_1_pins: i2c2-pins-g1 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2_1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe0_led0_pins: gbe0-pins {
|
||||
gbe0_led0_pins: gbe0-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe0_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe1_led0_pins: gbe1-pins {
|
||||
gbe1_led0_pins: gbe1-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe1_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe2_led0_pins: gbe2-pins {
|
||||
gbe2_led0_pins: gbe2-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe2_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe3_led0_pins: gbe3-pins {
|
||||
gbe3_led0_pins: gbe3-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe3_led0";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led0_pins: 2p5gbe-pins {
|
||||
gbe0_led1_pins: gbe0-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe0_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe1_led1_pins: gbe1-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe1_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe2_led1_pins: gbe2-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe2_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe3_led1_pins: gbe3-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe3_led1";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "2p5gbe_led0";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led1_pins: 2p5gbe-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "2p5gbe_led1";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_45";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_sdcard: mmc0-pins-sdcard {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "sdcard";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
|
|
@ -380,6 +465,8 @@
|
|||
<&infracfg CLK_INFRA_MUX_UART0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -645,6 +732,29 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7986-mmc",
|
||||
"mediatek,mt7981-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>,
|
||||
<0 0x11D60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
||||
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
||||
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
||||
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
||||
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
||||
clock-names = "source",
|
||||
"hclk",
|
||||
"axi_cg",
|
||||
"ahb_cg";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tphy: tphy@11c50000 {
|
||||
compatible = "mediatek,mt7988",
|
||||
"mediatek,generic-tphy-v2";
|
||||
|
|
@ -747,6 +857,157 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <ðrst 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy3>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p0>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy0_led0: gsw-phy0-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy0_led1: gsw-phy0-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p1>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy1_led0: gsw-phy1-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy1_led1: gsw-phy1-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <2>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p2>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy2_led0: gsw-phy2-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy2_led1: gsw-phy2-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <3>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p3>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy3_led0: gsw-phy3-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy3_led1: gsw-phy3-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethwarp: syscon@15031000 {
|
||||
|
|
@ -843,6 +1104,40 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gmac2: mac@2 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
mdio_bus: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* internal 2.5G PHY */
|
||||
int_2p5g_phy: ethernet-phy@15 {
|
||||
reg = <15>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "internal";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
|
||||
|
|
@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
|
||||
|
|
@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
|
||||
|
|
@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
|
||||
|
|
@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
|
||||
|
|
@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
|
|||
PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1),
|
||||
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
|
||||
|
|
@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
|
|||
PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1),
|
||||
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
|
||||
|
|
@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
|
||||
|
|
@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
|
||||
|
|
@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
|
||||
|
|
@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
|
||||
|
|
@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
|
||||
|
|
@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
|
||||
|
|
@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
/dts-v1/;
|
||||
#include "mt7988a-rfb-spim-nand.dtsi"
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
|
||||
|
|
@ -29,173 +30,105 @@
|
|||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
status = "okay";
|
||||
phy-mode = "internal";
|
||||
phy-connection-type = "internal";
|
||||
phy = <&int_2p5g_phy>;
|
||||
};
|
||||
|
||||
&gmac2 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-connection-type = "usxgmii";
|
||||
phy = <&phy8>;
|
||||
};
|
||||
|
||||
&mdio_bus {
|
||||
/* external Aquantia AQR113C */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 72 1>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
phy-connection-type = "internal";
|
||||
phy = <&phy15>;
|
||||
/* external Aquantia AQR113C */
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 71 1>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
|
||||
gmac2: mac@2 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <2>;
|
||||
phy-mode = "10gbase-kr";
|
||||
phy-connection-type = "10gbase-kr";
|
||||
phy = <&phy8>;
|
||||
/* external Maxlinear GPY211C */
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
mdio0: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* external Aquantia AQR113C */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 72 1>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
|
||||
/* external Aquantia AQR113C */
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 71 1>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
|
||||
/* external Maxlinear GPY211C */
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
/* external Maxlinear GPY211C */
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <13>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
/* internal 2.5G PHY */
|
||||
phy15: ethernet-phy@15 {
|
||||
reg = <15>;
|
||||
pinctrl-names = "i2p5gbe-led";
|
||||
pinctrl-0 = <&i2p5gbe_led0_pins>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "internal";
|
||||
};
|
||||
/* external Maxlinear GPY211C */
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <13>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
};
|
||||
|
||||
&int_2p5g_phy {
|
||||
pinctrl-names = "i2p5gbe-led";
|
||||
pinctrl-0 = <&i2p5gbe_led0_pins>;
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy3>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe0_led0_pins>;
|
||||
nvmem-cells = <&phy_calibration_p0>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
};
|
||||
|
||||
gsw_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe1_led0_pins>;
|
||||
nvmem-cells = <&phy_calibration_p1>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
};
|
||||
|
||||
gsw_phy2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <2>;
|
||||
phy-mode = "internal";
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe2_led0_pins>;
|
||||
nvmem-cells = <&phy_calibration_p2>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
};
|
||||
|
||||
gsw_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <3>;
|
||||
phy-mode = "internal";
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe3_led0_pins>;
|
||||
nvmem-cells = <&phy_calibration_p3>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsw_phy0 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe0_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy0_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy1 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe1_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy1_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy2 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe2_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy2_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy3 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe3_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy3_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,12 +4,13 @@
|
|||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/reset/ti-syscon.h>
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/reset/ti-syscon.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
|
|
@ -144,9 +145,9 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
/* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
reg = <0 0x43000000 0 0x50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
|
@ -228,7 +229,7 @@
|
|||
"iocfg_lb_base", "iocfg_tl_base", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 83>;
|
||||
gpio-ranges = <&pio 0 0 84>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
|
@ -260,47 +261,131 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins-g0 {
|
||||
i2c1_sfp_pins: i2c1-sfp-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c1_sfp";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins: i2c2-pins {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_0_pins: i2c2-pins-g0 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2_0";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_1_pins: i2c2-pins-g1 {
|
||||
mux {
|
||||
function = "i2c";
|
||||
groups = "i2c2_1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe0_led0_pins: gbe0-pins {
|
||||
gbe0_led0_pins: gbe0-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe0_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe1_led0_pins: gbe1-pins {
|
||||
gbe1_led0_pins: gbe1-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe1_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe2_led0_pins: gbe2-pins {
|
||||
gbe2_led0_pins: gbe2-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe2_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe3_led0_pins: gbe3-pins {
|
||||
gbe3_led0_pins: gbe3-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe3_led0";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led0_pins: 2p5gbe-pins {
|
||||
gbe0_led1_pins: gbe0-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe0_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe1_led1_pins: gbe1-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe1_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe2_led1_pins: gbe2-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe2_led1";
|
||||
};
|
||||
};
|
||||
|
||||
gbe3_led1_pins: gbe3-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe3_led1";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led0_pins: 2p5gbe-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "2p5gbe_led0";
|
||||
};
|
||||
};
|
||||
|
||||
i2p5gbe_led1_pins: 2p5gbe-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "2p5gbe_led1";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_45";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_sdcard: mmc0-pins-sdcard {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "sdcard";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
|
|
@ -380,6 +465,8 @@
|
|||
<&infracfg CLK_INFRA_MUX_UART0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -645,6 +732,29 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7986-mmc",
|
||||
"mediatek,mt7981-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>,
|
||||
<0 0x11D60000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
||||
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
||||
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
||||
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
||||
<&apmixedsys CLK_APMIXED_MSDCPLL>;
|
||||
clock-names = "source",
|
||||
"hclk",
|
||||
"axi_cg",
|
||||
"ahb_cg";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tphy: tphy@11c50000 {
|
||||
compatible = "mediatek,mt7988",
|
||||
"mediatek,generic-tphy-v2";
|
||||
|
|
@ -747,6 +857,157 @@
|
|||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <ðrst 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&gsw_phy3>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p0>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy0_led0: gsw-phy0-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy0_led1: gsw-phy0-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <1>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p1>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy1_led0: gsw-phy1-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy1_led1: gsw-phy1-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy2: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <2>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p2>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy2_led0: gsw-phy2-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy2_led1: gsw-phy2-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gsw_phy3: ethernet-phy@3 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
reg = <3>;
|
||||
phy-mode = "internal";
|
||||
nvmem-cells = <&phy_calibration_p3>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gsw_phy3_led0: gsw-phy3-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsw_phy3_led1: gsw-phy3-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethwarp: syscon@15031000 {
|
||||
|
|
@ -843,6 +1104,40 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "internal";
|
||||
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
gmac2: mac@2 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
mdio_bus: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* internal 2.5G PHY */
|
||||
int_2p5g_phy: ethernet-phy@15 {
|
||||
reg = <15>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "internal";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -46,37 +46,53 @@ static const struct mtk_pin_field_calc mt7988_pin_do_range[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1),
|
||||
|
|
@ -86,17 +102,31 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1),
|
||||
|
|
@ -104,42 +134,61 @@ static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1),
|
||||
|
|
@ -149,17 +198,31 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1),
|
||||
|
|
@ -167,8 +230,11 @@ static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
|
||||
|
|
@ -176,8 +242,11 @@ static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = {
|
|||
PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1),
|
||||
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1),
|
||||
|
|
@ -190,11 +259,19 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
|
|||
PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1),
|
||||
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1),
|
||||
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1),
|
||||
|
|
@ -203,26 +280,37 @@ static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3),
|
||||
PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3),
|
||||
|
|
@ -232,7 +320,8 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3),
|
||||
|
|
@ -242,17 +331,29 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3),
|
||||
|
|
@ -260,35 +361,49 @@ static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = {
|
|||
PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1),
|
||||
|
|
@ -298,46 +413,73 @@ static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1),
|
||||
|
|
@ -347,46 +489,73 @@ static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
|
||||
PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1),
|
||||
|
||||
PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1),
|
||||
|
||||
PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1),
|
||||
|
||||
PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1),
|
||||
|
|
@ -396,19 +565,35 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
|
|||
PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1),
|
||||
|
||||
PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1),
|
||||
|
||||
PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1),
|
||||
|
||||
PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1),
|
||||
|
||||
PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
|
||||
|
|
@ -1279,4 +1464,3 @@ static int __init mt7988_pinctrl_init(void)
|
|||
return platform_driver_register(&mt7988_pinctrl_driver);
|
||||
}
|
||||
arch_initcall(mt7988_pinctrl_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ FEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part lega
|
|||
SUBTARGETS:=cortexa9 cortexa53 cortexa72
|
||||
|
||||
KERNEL_PATCHVER:=5.15
|
||||
KERNEL_TESTING_PATCHVER:=6.1
|
||||
|
||||
include $(INCLUDE_DIR)/target.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,435 @@
|
|||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
CONFIG_ARCH_32BIT_OFF_T=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
|
||||
CONFIG_ARCH_MULTIPLATFORM=y
|
||||
CONFIG_ARCH_MULTI_V6_V7=y
|
||||
CONFIG_ARCH_MULTI_V7=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_ARCH_NR_GPIO=0
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARMADA_370_CLK=y
|
||||
CONFIG_ARMADA_370_XP_IRQ=y
|
||||
CONFIG_ARMADA_370_XP_TIMER=y
|
||||
# CONFIG_ARMADA_37XX_WATCHDOG is not set
|
||||
CONFIG_ARMADA_38X_CLK=y
|
||||
CONFIG_ARMADA_THERMAL=y
|
||||
CONFIG_ARMADA_XP_CLK=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
|
||||
# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARM_CRYPTO=y
|
||||
CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_ARM_ERRATA_764369=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GLOBAL_TIMER=y
|
||||
CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1
|
||||
CONFIG_ARM_HAS_SG_CHAIN=y
|
||||
CONFIG_ARM_HEAVY_MB=y
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=6
|
||||
CONFIG_ARM_L1_CACHE_SHIFT_6=y
|
||||
CONFIG_ARM_MVEBU_V7_CPUIDLE=y
|
||||
CONFIG_ARM_PATCH_IDIV=y
|
||||
CONFIG_ARM_PATCH_PHYS_VIRT=y
|
||||
CONFIG_ARM_THUMB=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_ARM_VIRT_EXT=y
|
||||
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_ATAGS=y
|
||||
CONFIG_ATA_LEDS=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BOUNCE=y
|
||||
# CONFIG_CACHE_FEROCEON_L2 is not set
|
||||
CONFIG_CACHE_L2X0=y
|
||||
CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_32v6K=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
CONFIG_CPU_CP15=y
|
||||
CONFIG_CPU_CP15_MMU=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_HAS_ASID=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_LADDER=y
|
||||
CONFIG_CPU_PABRT_V7=y
|
||||
CONFIG_CPU_PJ4B=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_SPECTRE=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CPU_THUMB_CAPABLE=y
|
||||
CONFIG_CPU_TLB_V7=y
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRYPTO_AES_ARM=y
|
||||
CONFIG_CRYPTO_AES_ARM_BS=y
|
||||
CONFIG_CRYPTO_AUTHENC=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
CONFIG_CRYPTO_DEV_MARVELL=y
|
||||
CONFIG_CRYPTO_DEV_MARVELL_CESA=y
|
||||
CONFIG_CRYPTO_ESSIV=y
|
||||
CONFIG_CRYPTO_HASH_INFO=y
|
||||
CONFIG_CRYPTO_HW=y
|
||||
CONFIG_CRYPTO_LIB_DES=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SHA1=y
|
||||
CONFIG_CRYPTO_SHA1_ARM=y
|
||||
CONFIG_CRYPTO_SHA1_ARM_NEON=y
|
||||
CONFIG_CRYPTO_SHA256_ARM=y
|
||||
CONFIG_CRYPTO_SHA512_ARM=y
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_ALIGN_RODATA=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_LL=y
|
||||
CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
|
||||
CONFIG_DEBUG_MVEBU_UART0=y
|
||||
# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
|
||||
# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
|
||||
CONFIG_DEBUG_UART_8250=y
|
||||
CONFIG_DEBUG_UART_8250_SHIFT=2
|
||||
CONFIG_DEBUG_UART_PHYS=0xd0012000
|
||||
CONFIG_DEBUG_UART_VIRT=0xfec12000
|
||||
CONFIG_DEBUG_UNCOMPRESS=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_ENGINE_RAID=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_OPS=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_EARLY_PRINTK=y
|
||||
CONFIG_EDAC_ATOMIC_SCRUB=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GENERIC_VDSO_32=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_MVEBU=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
CONFIG_GPIO_PCA953X_IRQ=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HWBM=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_HZ_PERIODIC=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
# CONFIG_I2C_PXA is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_IWMMXT is not set
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_KMAP_LOCAL=y
|
||||
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PCA963X=y
|
||||
CONFIG_LEDS_TLC591XX=y
|
||||
CONFIG_LEDS_TRIGGER_DISK=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MACH_ARMADA_370=y
|
||||
# CONFIG_MACH_ARMADA_375 is not set
|
||||
CONFIG_MACH_ARMADA_38X=y
|
||||
# CONFIG_MACH_ARMADA_39X is not set
|
||||
CONFIG_MACH_ARMADA_XP=y
|
||||
# CONFIG_MACH_DOVE is not set
|
||||
CONFIG_MACH_MVEBU_ANY=y
|
||||
CONFIG_MACH_MVEBU_V7=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MANGLE_BOOTARGS=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MDIO_I2C=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_MVSDIO=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_PXAV3=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
CONFIG_MTD_NAND_MARVELL=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_MVEBU_CLK_COMMON=y
|
||||
CONFIG_MVEBU_CLK_COREDIV=y
|
||||
CONFIG_MVEBU_CLK_CPU=y
|
||||
CONFIG_MVEBU_DEVBUS=y
|
||||
CONFIG_MVEBU_MBUS=y
|
||||
CONFIG_MVMDIO=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MVNETA_BM=y
|
||||
CONFIG_MVNETA_BM_ENABLE=y
|
||||
# CONFIG_MVPP2 is not set
|
||||
CONFIG_MV_XOR=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
CONFIG_NET_DSA_MV88E6XXX=y
|
||||
CONFIG_NET_DSA_TAG_DSA=y
|
||||
CONFIG_NET_DSA_TAG_DSA_COMMON=y
|
||||
CONFIG_NET_DSA_TAG_EDSA=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_ORION_WATCHDOG=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_BRIDGE_EMUL=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=2
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
|
||||
# CONFIG_PHY_MVEBU_A3700_UTMI is not set
|
||||
# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
|
||||
# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
|
||||
# CONFIG_PHY_MVEBU_CP110_UTMI is not set
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_370=y
|
||||
CONFIG_PINCTRL_ARMADA_38X=y
|
||||
CONFIG_PINCTRL_ARMADA_XP=y
|
||||
CONFIG_PINCTRL_MVEBU=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PJ4B_ERRATA_4742=y
|
||||
CONFIG_PL310_ERRATA_753970=y
|
||||
CONFIG_PLAT_ORION=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_ARMADA38X=y
|
||||
# CONFIG_RTC_DRV_MV is not set
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_MC146818_LIB=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_SATA_HOST=y
|
||||
CONFIG_SATA_MV=y
|
||||
CONFIG_SATA_PMP=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
CONFIG_SENSORS_PWM_FAN=y
|
||||
CONFIG_SENSORS_TMP421=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_MVEBU_CONSOLE=y
|
||||
CONFIG_SERIAL_MVEBU_UART=y
|
||||
CONFIG_SFP=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SOC_BUS=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
# CONFIG_SPI_ARMADA_3700 is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ORION=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRAM_EXEC=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_UNWINDER_ARM=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_ORION=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_LEDS_TRIGGER_USBPORT=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_MVEBU=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=39
|
||||
CONFIG_ARM64_VA_BITS_39=y
|
||||
CONFIG_ARMADA_37XX_CLK=y
|
||||
CONFIG_ARMADA_37XX_RWTM_MBOX=y
|
||||
CONFIG_ARMADA_37XX_WATCHDOG=y
|
||||
CONFIG_ARMADA_AP806_SYSCON=y
|
||||
CONFIG_ARMADA_AP_CP_HELPER=y
|
||||
CONFIG_ARMADA_CP110_SYSCON=y
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
|
||||
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
# CONFIG_ARM_MHU_V2 is not set
|
||||
# CONFIG_ARM_PL172_MPMC is not set
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_FIND_FIRST_BIT=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MMC_SDHCI_XENON=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MVEBU_GICP=y
|
||||
CONFIG_MVEBU_ICU=y
|
||||
CONFIG_MVEBU_ODMI=y
|
||||
CONFIG_MVEBU_PIC=y
|
||||
CONFIG_MVEBU_SEI=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI_AARDVARK=y
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_MVEBU_A3700_COMPHY=y
|
||||
CONFIG_PHY_MVEBU_A3700_UTMI=y
|
||||
CONFIG_PINCTRL_ARMADA_37XX=y
|
||||
CONFIG_PINCTRL_ARMADA_AP806=y
|
||||
CONFIG_PINCTRL_ARMADA_CP110=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPI_ARMADA_3700=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TURRIS_MOX_RWTM=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_AQUANTIA_PHY=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_1742098=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_TAGGED_ADDR_ABI is not set
|
||||
CONFIG_ARM64_VA_BITS=39
|
||||
CONFIG_ARM64_VA_BITS_39=y
|
||||
CONFIG_ARMADA_37XX_CLK=y
|
||||
CONFIG_ARMADA_AP806_SYSCON=y
|
||||
CONFIG_ARMADA_AP_CPU_CLK=y
|
||||
CONFIG_ARMADA_AP_CP_HELPER=y
|
||||
CONFIG_ARMADA_CP110_SYSCON=y
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
|
||||
CONFIG_ARM_ARMADA_8K_CPUFREQ=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
# CONFIG_ARM_PL172_MPMC is not set
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_FIND_FIRST_BIT=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_HW_RANDOM_OMAP=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_LEDS_IEI_WT61P803_PUZZLE=y
|
||||
CONFIG_LEDS_IS31FL319X=y
|
||||
CONFIG_MARVELL_10G_PHY=y
|
||||
CONFIG_MFD_CORE=y
|
||||
CONFIG_MFD_IEI_WT61P803_PUZZLE=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MMC_SDHCI_XENON=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MVEBU_GICP=y
|
||||
CONFIG_MVEBU_ICU=y
|
||||
CONFIG_MVEBU_ODMI=y
|
||||
CONFIG_MVEBU_PIC=y
|
||||
CONFIG_MVEBU_SEI=y
|
||||
CONFIG_MVPP2=y
|
||||
CONFIG_MV_XOR_V2=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_ARMADA_8K=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
# CONFIG_PCI_AARDVARK is not set
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_MVEBU_CP110_COMPHY=y
|
||||
CONFIG_PINCTRL_ARMADA_37XX=y
|
||||
CONFIG_PINCTRL_ARMADA_AP806=y
|
||||
CONFIG_PINCTRL_ARMADA_CP110=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_RAS=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set
|
||||
CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_LED_TRIGGER_PHY=y
|
||||
CONFIG_PHY_MVEBU_A38X_COMPHY=y
|
||||
CONFIG_RTC_DRV_MV=y
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
From 81c0004a6433ff90fa6129418802c3c367e453c2 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
|
||||
Date: Mon, 4 Jul 2022 13:36:21 +0200
|
||||
Subject: [PATCH 1/5] ARM: dts: turris-omnia: configure LED[0] pin function to
|
||||
link/activity
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The marvell PHY driver changes the LED[0] pin function to "On - 1000
|
||||
Mbps Link, Off - Else".
|
||||
|
||||
Turris Omnia expects that the function is "On - Link, Blink - Activity,
|
||||
Off - No link".
|
||||
|
||||
Use the `marvell,reg-init` DT property to change the function.
|
||||
|
||||
In the future, once netdev trigger will support HW offloading, we will
|
||||
be able to have this configured via the combination of PHY driver and
|
||||
leds-turris-omnia driver.
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
|
||||
@@ -396,7 +396,8 @@
|
||||
phy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
- marvell,reg-init = <3 18 0 0x4985>;
|
||||
+ marvell,reg-init = <3 18 0 0x4985>,
|
||||
+ <3 16 0xfff0 0x0001>;
|
||||
|
||||
/* irq is connected to &pcawan pin 7 */
|
||||
};
|
||||
|
|
@ -48,7 +48,7 @@ Cc: stable@vger.kernel.org
|
|||
|
||||
--- a/drivers/pci/controller/pci-aardvark.c
|
||||
+++ b/drivers/pci/controller/pci-aardvark.c
|
||||
@@ -210,6 +210,8 @@ enum {
|
||||
@@ -212,6 +212,8 @@ enum {
|
||||
};
|
||||
|
||||
#define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
|
||||
|
|
@ -57,7 +57,7 @@ Cc: stable@vger.kernel.org
|
|||
|
||||
/* PCIe core controller registers */
|
||||
#define CTRL_CORE_BASE_ADDR 0x18000
|
||||
@@ -558,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad
|
||||
@@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
|
||||
PCIE_CORE_CTRL2_TD_ENABLE;
|
||||
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ Cc: stable@vger.kernel.org
|
|||
/* Set lane X1 */
|
||||
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
||||
reg &= ~LANE_CNT_MSK;
|
||||
@@ -1580,6 +1587,9 @@ static irqreturn_t advk_pcie_irq_handler
|
||||
@@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
|
||||
struct advk_pcie *pcie = arg;
|
||||
u32 status;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,48 +0,0 @@
|
|||
From fed7cef5e4f2df8c6a79bebf5da1fdd3783ff6f3 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
|
||||
Date: Mon, 4 Jul 2022 13:36:22 +0200
|
||||
Subject: [PATCH] ARM: dts: turris-omnia: enable LED controller node
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The LED controller node is disabled because the leds-turris-omnia driver
|
||||
does not support setting the LED blinking to be controlled by the MCU.
|
||||
|
||||
The patches for that have now been sent [1], so let's enable the node.
|
||||
|
||||
[1] https://lore.kernel.org/linux-leds/20220704105955.15474-1-kabel@kernel.org/T/
|
||||
|
||||
Signed-off-by: Marek Behún <kabel@kernel.org>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-turris-omnia.dts | 7 ++-----
|
||||
1 file changed, 2 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
|
||||
@@ -194,15 +194,13 @@
|
||||
reg = <0x2b>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+ status = "okay";
|
||||
|
||||
/*
|
||||
* LEDs are controlled by MCU (STM32F0) at
|
||||
* address 0x2b.
|
||||
*
|
||||
- * The driver does not support HW control mode
|
||||
- * for the LEDs yet. Disable the LEDs for now.
|
||||
- *
|
||||
- * Also LED functions are not stable yet:
|
||||
+ * LED functions are not stable yet:
|
||||
* - there are 3 LEDs connected via MCU to PCIe
|
||||
* ports. One of these ports supports mSATA.
|
||||
* There is no mSATA nor PCIe function.
|
||||
@@ -213,7 +211,6 @@
|
||||
* B. Again there is no such function defined.
|
||||
* For now we use LED_FUNCTION_INDICATOR
|
||||
*/
|
||||
- status = "disabled";
|
||||
|
||||
multi-led@0 {
|
||||
reg = <0x0>;
|
||||
|
|
@ -28,7 +28,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|||
|
||||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
||||
@@ -1586,6 +1586,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
||||
The command-line arguments provided by the boot loader will be
|
||||
appended to the the device tree bootargs property.
|
||||
|
||||
|
|
@ -258,7 +258,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|||
static int kernel_init(void *);
|
||||
|
||||
extern void init_IRQ(void);
|
||||
@@ -991,6 +995,18 @@ asmlinkage __visible void __init __no_sa
|
||||
@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa
|
||||
page_alloc_init();
|
||||
|
||||
pr_notice("Kernel command line: %s\n", saved_command_line);
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/mach-mvebu/Kconfig
|
||||
+++ b/arch/arm/mach-mvebu/Kconfig
|
||||
@@ -67,6 +67,7 @@ config MACH_ARMADA_38X
|
||||
@@ -66,6 +66,7 @@ config MACH_ARMADA_38X
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select MACH_MVEBU_V7
|
||||
select PINCTRL_ARMADA_38X
|
||||
|
|
|
|||
|
|
@ -667,7 +667,7 @@
|
|||
pinctrl-0 = <&sdhci_pins>;
|
||||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -225,12 +225,100 @@
|
||||
@@ -223,12 +223,100 @@
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
|
|||
|
||||
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
---
|
||||
arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
|
||||
1 file changed, 15 insertions(+)
|
||||
arch/arm/boot/dts/armada-385-db-ap.dts | 6 +++---
|
||||
1 file changed, 3 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -485,3 +485,7 @@
|
||||
@@ -483,3 +483,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -387,7 +387,7 @@
|
||||
@@ -385,7 +385,7 @@
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
@@ -197,7 +204,7 @@
|
||||
@@ -195,7 +202,7 @@
|
||||
pinctrl-0 = <&power_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
|
|||
|
||||
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
||||
---
|
||||
arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
|
||||
.../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
|
||||
.../arm/boot/dts/armada-388-clearfog-base.dts | 1 +
|
||||
.../armada-38x-solidrun-microsom-emmc.dtsi | 62 +++++++++++++++++++
|
||||
2 files changed, 63 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ Signed-off-by: Tad Davanzo <tad@spotco.us>
|
|||
|
||||
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
||||
@@ -456,9 +456,9 @@
|
||||
@@ -454,9 +454,9 @@
|
||||
reg = <0xa00000 0x2800000>; /* 40MB */
|
||||
};
|
||||
|
||||
|
|
@ -23,7 +23,7 @@ Signed-off-by: Tad Davanzo <tad@spotco.us>
|
|||
};
|
||||
|
||||
/* kernel2 overlaps with rootfs2 by design */
|
||||
@@ -467,9 +467,9 @@
|
||||
@@ -465,9 +465,9 @@
|
||||
reg = <0x3200000 0x2800000>; /* 40MB */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/arch/arm/boot/dts/armada-370.dtsi
|
||||
+++ b/arch/arm/boot/dts/armada-370.dtsi
|
||||
@@ -234,7 +234,7 @@
|
||||
@@ -254,7 +254,7 @@
|
||||
clocks = <&gateclk 23>;
|
||||
clock-names = "cesa0";
|
||||
marvell,crypto-srams = <&crypto_sram>;
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
@@ -255,12 +255,17 @@
|
||||
@@ -275,12 +275,17 @@
|
||||
* cpuidle workaround.
|
||||
*/
|
||||
idle-sram@0 {
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|||
---
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -5006,6 +5006,16 @@ static int mvneta_setup_tc(struct net_de
|
||||
@@ -5222,6 +5222,16 @@ static int mvneta_setup_tc(struct net_de
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -26,7 +26,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|||
static const struct net_device_ops mvneta_netdev_ops = {
|
||||
.ndo_open = mvneta_open,
|
||||
.ndo_stop = mvneta_stop,
|
||||
@@ -5016,6 +5026,9 @@ static const struct net_device_ops mvnet
|
||||
@@ -5232,6 +5242,9 @@ static const struct net_device_ops mvnet
|
||||
.ndo_fix_features = mvneta_fix_features,
|
||||
.ndo_get_stats64 = mvneta_get_stats64,
|
||||
.ndo_eth_ioctl = mvneta_ioctl,
|
||||
|
|
|
|||
|
|
@ -1,66 +0,0 @@
|
|||
From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Date: Fri, 26 Nov 2021 12:20:53 +0100
|
||||
Subject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio
|
||||
configuration
|
||||
|
||||
The struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt,
|
||||
that allows passing extra parameters, such as traffic shaping. This commit
|
||||
converts the current mqprio code to that new struct.
|
||||
|
||||
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++-------
|
||||
1 file changed, 10 insertions(+), 7 deletions(-)
|
||||
|
||||
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -38,6 +38,7 @@
|
||||
#include <net/ipv6.h>
|
||||
#include <net/tso.h>
|
||||
#include <net/page_pool.h>
|
||||
+#include <net/pkt_cls.h>
|
||||
#include <linux/bpf_trace.h>
|
||||
|
||||
/* Registers */
|
||||
@@ -4966,14 +4967,14 @@ static void mvneta_setup_rx_prio_map(str
|
||||
}
|
||||
|
||||
static int mvneta_setup_mqprio(struct net_device *dev,
|
||||
- struct tc_mqprio_qopt *qopt)
|
||||
+ struct tc_mqprio_qopt_offload *mqprio)
|
||||
{
|
||||
struct mvneta_port *pp = netdev_priv(dev);
|
||||
u8 num_tc;
|
||||
int i;
|
||||
|
||||
- qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
|
||||
- num_tc = qopt->num_tc;
|
||||
+ mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
|
||||
+ num_tc = mqprio->qopt.num_tc;
|
||||
|
||||
if (num_tc > rxq_number)
|
||||
return -EINVAL;
|
||||
@@ -4984,13 +4985,15 @@ static int mvneta_setup_mqprio(struct ne
|
||||
return 0;
|
||||
}
|
||||
|
||||
- memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));
|
||||
+ memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
|
||||
+ sizeof(pp->prio_tc_map));
|
||||
|
||||
mvneta_setup_rx_prio_map(pp);
|
||||
|
||||
- netdev_set_num_tc(dev, qopt->num_tc);
|
||||
- for (i = 0; i < qopt->num_tc; i++)
|
||||
- netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);
|
||||
+ netdev_set_num_tc(dev, mqprio->qopt.num_tc);
|
||||
+ for (i = 0; i < mqprio->qopt.num_tc; i++)
|
||||
+ netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
|
||||
+ mqprio->qopt.offset[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Date: Fri, 26 Nov 2021 12:20:54 +0100
|
||||
Subject: net: mvneta: Don't force-set the offloading flag
|
||||
|
||||
The qopt->hw flag is set by the TC code according to the offloading mode
|
||||
asked by user. Don't force-set it in the driver, but instead read it to
|
||||
make sure we do what's asked.
|
||||
|
||||
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -4973,7 +4973,9 @@ static int mvneta_setup_mqprio(struct ne
|
||||
u8 num_tc;
|
||||
int i;
|
||||
|
||||
- mqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;
|
||||
+ if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
|
||||
+ return 0;
|
||||
+
|
||||
num_tc = mqprio->qopt.num_tc;
|
||||
|
||||
if (num_tc > rxq_number)
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Date: Fri, 26 Nov 2021 12:20:55 +0100
|
||||
Subject: net: mvneta: Allow having more than one queue per TC
|
||||
|
||||
The current mqprio implementation assumed that we are only using one
|
||||
queue per TC. Use the offset and count parameters to allow using
|
||||
multiple queues per TC. In that case, the controller will use a standard
|
||||
round-robin algorithm to pick queues assigned to the same TC, with the
|
||||
same priority.
|
||||
|
||||
This only applies to VLAN priorities in ingress traffic, each TC
|
||||
corresponding to a vlan priority.
|
||||
|
||||
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++---------------
|
||||
1 file changed, 20 insertions(+), 15 deletions(-)
|
||||
|
||||
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -498,7 +498,6 @@ struct mvneta_port {
|
||||
u8 mcast_count[256];
|
||||
u16 tx_ring_size;
|
||||
u16 rx_ring_size;
|
||||
- u8 prio_tc_map[8];
|
||||
|
||||
phy_interface_t phy_interface;
|
||||
struct device_node *dn;
|
||||
@@ -4955,13 +4954,12 @@ static void mvneta_clear_rx_prio_map(str
|
||||
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);
|
||||
}
|
||||
|
||||
-static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
|
||||
+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)
|
||||
{
|
||||
- u32 val = 0;
|
||||
- int i;
|
||||
+ u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);
|
||||
|
||||
- for (i = 0; i < rxq_number; i++)
|
||||
- val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);
|
||||
+ val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);
|
||||
+ val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);
|
||||
|
||||
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
|
||||
}
|
||||
@@ -4970,8 +4968,8 @@ static int mvneta_setup_mqprio(struct ne
|
||||
struct tc_mqprio_qopt_offload *mqprio)
|
||||
{
|
||||
struct mvneta_port *pp = netdev_priv(dev);
|
||||
+ int rxq, tc;
|
||||
u8 num_tc;
|
||||
- int i;
|
||||
|
||||
if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
|
||||
return 0;
|
||||
@@ -4981,21 +4979,28 @@ static int mvneta_setup_mqprio(struct ne
|
||||
if (num_tc > rxq_number)
|
||||
return -EINVAL;
|
||||
|
||||
+ mvneta_clear_rx_prio_map(pp);
|
||||
+
|
||||
if (!num_tc) {
|
||||
- mvneta_clear_rx_prio_map(pp);
|
||||
netdev_reset_tc(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
- memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,
|
||||
- sizeof(pp->prio_tc_map));
|
||||
+ netdev_set_num_tc(dev, mqprio->qopt.num_tc);
|
||||
|
||||
- mvneta_setup_rx_prio_map(pp);
|
||||
+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
|
||||
+ netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],
|
||||
+ mqprio->qopt.offset[tc]);
|
||||
+
|
||||
+ for (rxq = mqprio->qopt.offset[tc];
|
||||
+ rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
|
||||
+ rxq++) {
|
||||
+ if (rxq >= rxq_number)
|
||||
+ return -EINVAL;
|
||||
|
||||
- netdev_set_num_tc(dev, mqprio->qopt.num_tc);
|
||||
- for (i = 0; i < mqprio->qopt.num_tc; i++)
|
||||
- netdev_set_tc_queue(dev, i, mqprio->qopt.count[i],
|
||||
- mqprio->qopt.offset[i]);
|
||||
+ mvneta_map_vlan_prio_to_rxq(pp, tc, rxq);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,182 +0,0 @@
|
|||
From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001
|
||||
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Date: Fri, 26 Nov 2021 12:20:56 +0100
|
||||
Subject: net: mvneta: Add TC traffic shaping offload
|
||||
|
||||
The mvneta controller is able to do some tocken-bucket per-queue traffic
|
||||
shaping. This commit adds support for setting these using the TC mqprio
|
||||
interface.
|
||||
|
||||
The token-bucket parameters are customisable, but the current
|
||||
implementation configures them to have a 10kbps resolution for the
|
||||
rate limitation, since it allows to cover the whole range of max_rate
|
||||
values from 10kbps to 5Gbps with 10kbps increments.
|
||||
|
||||
Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 119 insertions(+), 1 deletion(-)
|
||||
|
||||
(limited to 'drivers/net/ethernet/marvell/mvneta.c')
|
||||
|
||||
--- a/drivers/net/ethernet/marvell/mvneta.c
|
||||
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
||||
@@ -248,12 +248,39 @@
|
||||
#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
|
||||
#define MVNETA_PORT_TX_RESET 0x3cf0
|
||||
#define MVNETA_PORT_TX_DMA_RESET BIT(0)
|
||||
+#define MVNETA_TXQ_CMD1_REG 0x3e00
|
||||
+#define MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 BIT(3)
|
||||
+#define MVNETA_TXQ_CMD1_BW_LIM_EN BIT(0)
|
||||
+#define MVNETA_REFILL_NUM_CLK_REG 0x3e08
|
||||
+#define MVNETA_REFILL_MAX_NUM_CLK 0x0000ffff
|
||||
#define MVNETA_TX_MTU 0x3e0c
|
||||
#define MVNETA_TX_TOKEN_SIZE 0x3e14
|
||||
#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_REG(q) (0x3e20 + ((q) << 2))
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK 0x3ff00000
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT 20
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX 0x0007ffff
|
||||
#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
|
||||
#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
|
||||
|
||||
+/* The values of the bucket refill base period and refill period are taken from
|
||||
+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows
|
||||
+ * to cover all rate-limit values from 10Kbps up to 5Gbps
|
||||
+ */
|
||||
+
|
||||
+/* Base period for the rate limit algorithm */
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS 100
|
||||
+
|
||||
+/* Number of Base Period to wait between each bucket refill */
|
||||
+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD 1000
|
||||
+
|
||||
+/* The base resolution for rate limiting, in bps. Any max_rate value should be
|
||||
+ * a multiple of that value.
|
||||
+ */
|
||||
+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \
|
||||
+ (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
|
||||
+ MVNETA_TXQ_BUCKET_REFILL_PERIOD))
|
||||
+
|
||||
#define MVNETA_LPI_CTRL_0 0x2cc0
|
||||
#define MVNETA_LPI_CTRL_1 0x2cc4
|
||||
#define MVNETA_LPI_REQUEST_ENABLE BIT(0)
|
||||
@@ -4964,11 +4991,74 @@ static void mvneta_map_vlan_prio_to_rxq(
|
||||
mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);
|
||||
}
|
||||
|
||||
+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)
|
||||
+{
|
||||
+ unsigned long core_clk_rate;
|
||||
+ u32 refill_cycles;
|
||||
+ u32 val;
|
||||
+
|
||||
+ core_clk_rate = clk_get_rate(pp->clk);
|
||||
+ if (!core_clk_rate)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /
|
||||
+ (NSEC_PER_SEC / core_clk_rate);
|
||||
+
|
||||
+ if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ /* Enable bw limit algorithm version 3 */
|
||||
+ val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
|
||||
+ val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
|
||||
+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
|
||||
+
|
||||
+ /* Set the base refill rate */
|
||||
+ mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)
|
||||
+{
|
||||
+ u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);
|
||||
+
|
||||
+ val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);
|
||||
+ mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);
|
||||
+}
|
||||
+
|
||||
+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,
|
||||
+ u64 min_rate, u64 max_rate)
|
||||
+{
|
||||
+ u32 refill_val, rem;
|
||||
+ u32 val = 0;
|
||||
+
|
||||
+ /* Convert to from Bps to bps */
|
||||
+ max_rate *= 8;
|
||||
+
|
||||
+ if (min_rate)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,
|
||||
+ &rem);
|
||||
+
|
||||
+ if (rem || !refill_val ||
|
||||
+ refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ val = refill_val;
|
||||
+ val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<
|
||||
+ MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);
|
||||
+
|
||||
+ mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int mvneta_setup_mqprio(struct net_device *dev,
|
||||
struct tc_mqprio_qopt_offload *mqprio)
|
||||
{
|
||||
struct mvneta_port *pp = netdev_priv(dev);
|
||||
- int rxq, tc;
|
||||
+ int rxq, txq, tc, ret;
|
||||
u8 num_tc;
|
||||
|
||||
if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)
|
||||
@@ -4982,6 +5072,7 @@ static int mvneta_setup_mqprio(struct ne
|
||||
mvneta_clear_rx_prio_map(pp);
|
||||
|
||||
if (!num_tc) {
|
||||
+ mvneta_disable_per_queue_rate_limit(pp);
|
||||
netdev_reset_tc(dev);
|
||||
return 0;
|
||||
}
|
||||
@@ -5002,6 +5093,33 @@ static int mvneta_setup_mqprio(struct ne
|
||||
}
|
||||
}
|
||||
|
||||
+ if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {
|
||||
+ mvneta_disable_per_queue_rate_limit(pp);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ if (mqprio->qopt.num_tc > txq_number)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ret = mvneta_enable_per_queue_rate_limit(pp);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ for (tc = 0; tc < mqprio->qopt.num_tc; tc++) {
|
||||
+ for (txq = mqprio->qopt.offset[tc];
|
||||
+ txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];
|
||||
+ txq++) {
|
||||
+ if (txq >= txq_number)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ret = mvneta_setup_queue_rates(pp, txq,
|
||||
+ mqprio->min_rate[tc],
|
||||
+ mqprio->max_rate[tc]);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From b01d622d76134e9401970ffd3fbbb9a7051f976a Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
||||
Date: Tue, 20 Sep 2022 14:11:54 +0200
|
||||
Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Reset COMPHY registers
|
||||
before USB 3.0 power on
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Turris MOX board with older ARM Trusted Firmware version v1.5 is not able
|
||||
to detect any USB 3.0 device connected to USB-A port on Mox-A module after
|
||||
commit 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken
|
||||
reset support"). On the other hand USB 2.0 devices connected to the same
|
||||
USB-A port are working fine.
|
||||
|
||||
It looks as if the older firmware configures COMPHY registers for USB 3.0
|
||||
somehow incompatibly for kernel driver. Experiments show that resetting
|
||||
COMPHY registers via setting SFT_RST auto-clearing bit in COMPHY_SFT_RESET
|
||||
register fixes this issue.
|
||||
|
||||
Reset the COMPHY in mvebu_a3700_comphy_usb3_power_on() function as a first
|
||||
step after selecting COMPHY lane and USB 3.0 function. With this change
|
||||
Turris MOX board can successfully detect USB 3.0 devices again.
|
||||
|
||||
Before the above mentioned commit this reset was implemented in PHY reset
|
||||
method, so this is the reason why there was no issue with older firmware
|
||||
version then.
|
||||
|
||||
Fixes: 0a6fc70d76bd ("phy: marvell: phy-mvebu-a3700-comphy: Remove broken reset support")
|
||||
Reported-by: Marek Behún <kabel@kernel.org>
|
||||
Signed-off-by: Pali Rohár <pali@kernel.org>
|
||||
Tested-by: Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>
|
||||
Link: https://lore.kernel.org/r/20220920121154.30115-1-pali@kernel.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
||||
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
||||
@@ -826,6 +826,9 @@ mvebu_a3700_comphy_usb3_power_on(struct
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ /* COMPHY register reset (cleared automatically) */
|
||||
+ comphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);
|
||||
+
|
||||
/*
|
||||
* 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
|
||||
* register belong to UTMI module, so it is set in UTMI phy driver.
|
||||
|
|
@ -13,7 +13,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|||
|
||||
--- a/drivers/pci/controller/pci-mvebu.c
|
||||
+++ b/drivers/pci/controller/pci-mvebu.c
|
||||
@@ -1023,6 +1023,7 @@ static int mvebu_pcie_powerup(struct mve
|
||||
@@ -1414,6 +1414,7 @@ static int mvebu_pcie_powerup(struct mve
|
||||
|
||||
if (port->reset_gpio) {
|
||||
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
||||
|
|
@ -21,7 +21,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|||
|
||||
of_property_read_u32(port->dn, "reset-delay-us",
|
||||
&reset_udelay);
|
||||
@@ -1030,7 +1031,13 @@ static int mvebu_pcie_powerup(struct mve
|
||||
@@ -1421,7 +1422,13 @@ static int mvebu_pcie_powerup(struct mve
|
||||
udelay(100);
|
||||
|
||||
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
||||
|
|
@ -36,7 +36,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|||
}
|
||||
|
||||
return 0;
|
||||
@@ -1190,15 +1197,16 @@ static int mvebu_pcie_probe(struct platf
|
||||
@@ -1538,15 +1545,16 @@ static int mvebu_pcie_probe(struct platf
|
||||
if (!child)
|
||||
continue;
|
||||
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
+ };
|
||||
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
|
||||
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
|
||||
@@ -519,6 +519,8 @@ patternProperties:
|
||||
@@ -579,6 +579,8 @@ patternProperties:
|
||||
description: IC Plus Corp.
|
||||
"^idt,.*":
|
||||
description: Integrated Device Technologies, Inc.
|
||||
|
|
|
|||
|
|
@ -16,17 +16,17 @@ Signed-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>
|
|||
Cc: Luka Perkov <luka.perkov@sartura.hr>
|
||||
Cc: Robert Marko <robert.marko@sartura.hr>
|
||||
---
|
||||
drivers/mfd/Kconfig | 8 +
|
||||
drivers/mfd/Kconfig | 9 +
|
||||
drivers/mfd/Makefile | 1 +
|
||||
drivers/mfd/iei-wt61p803-puzzle.c | 908 ++++++++++++++++++++++++
|
||||
include/linux/mfd/iei-wt61p803-puzzle.h | 66 ++
|
||||
4 files changed, 983 insertions(+)
|
||||
4 files changed, 984 insertions(+)
|
||||
create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c
|
||||
create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h
|
||||
|
||||
--- a/drivers/mfd/Kconfig
|
||||
+++ b/drivers/mfd/Kconfig
|
||||
@@ -2189,6 +2189,15 @@ config SGI_MFD_IOC3
|
||||
@@ -2221,6 +2221,15 @@ config SGI_MFD_IOC3
|
||||
If you have an SGI Origin, Octane, or a PCI IOC3 card,
|
||||
then say Y. Otherwise say N.
|
||||
|
||||
|
|
@ -44,14 +44,14 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
depends on SPI_MASTER
|
||||
--- a/drivers/mfd/Makefile
|
||||
+++ b/drivers/mfd/Makefile
|
||||
@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_DLN2) += dln2.o
|
||||
obj-$(CONFIG_MFD_RT4831) += rt4831.o
|
||||
@@ -244,6 +244,7 @@ obj-$(CONFIG_MFD_RT4831) += rt4831.o
|
||||
obj-$(CONFIG_MFD_RT5033) += rt5033.o
|
||||
obj-$(CONFIG_MFD_RT5120) += rt5120.o
|
||||
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
|
||||
+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o
|
||||
+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE) += iei-wt61p803-puzzle.o
|
||||
|
||||
intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
|
||||
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
|
||||
obj-$(CONFIG_INTEL_SOC_PMIC) += intel_soc_pmic_crc.o
|
||||
obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/mfd/iei-wt61p803-puzzle.c
|
||||
@@ -0,0 +1,908 @@
|
||||
|
|
|
|||
|
|
@ -20,13 +20,13 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
---
|
||||
drivers/hwmon/Kconfig | 8 +
|
||||
drivers/hwmon/Makefile | 1 +
|
||||
drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++
|
||||
3 files changed, 422 insertions(+)
|
||||
drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 445 ++++++++++++++++++++++
|
||||
3 files changed, 454 insertions(+)
|
||||
create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
|
||||
|
||||
--- a/drivers/hwmon/Kconfig
|
||||
+++ b/drivers/hwmon/Kconfig
|
||||
@@ -732,6 +732,14 @@ config SENSORS_IBMPOWERNV
|
||||
@@ -755,6 +755,14 @@ config SENSORS_IBMPOWERNV
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called ibmpowernv.
|
||||
|
||||
|
|
@ -43,7 +43,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
depends on IIO
|
||||
--- a/drivers/hwmon/Makefile
|
||||
+++ b/drivers/hwmon/Makefile
|
||||
@@ -84,6 +84,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
|
||||
@@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_HIH6130) += hih6130
|
||||
obj-$(CONFIG_SENSORS_ULTRA45) += ultra45_env.o
|
||||
obj-$(CONFIG_SENSORS_I5500) += i5500_temp.o
|
||||
obj-$(CONFIG_SENSORS_I5K_AMB) += i5k_amb.o
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
|
||||
--- a/drivers/leds/Kconfig
|
||||
+++ b/drivers/leds/Kconfig
|
||||
@@ -306,6 +306,14 @@ config LEDS_IPAQ_MICRO
|
||||
@@ -299,6 +299,14 @@ config LEDS_IPAQ_MICRO
|
||||
Choose this option if you want to use the notification LED on
|
||||
Compaq/HP iPAQ h3100 and h3600.
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
depends on LEDS_CLASS
|
||||
--- a/drivers/leds/Makefile
|
||||
+++ b/drivers/leds/Makefile
|
||||
@@ -33,6 +33,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
|
||||
@@ -32,6 +32,7 @@ obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.
|
||||
obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o
|
||||
obj-$(CONFIG_LEDS_IP30) += leds-ip30.o
|
||||
obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o
|
||||
|
|
|
|||
|
|
@ -64,11 +64,11 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
+================= == =====================================================
|
||||
--- a/Documentation/hwmon/index.rst
|
||||
+++ b/Documentation/hwmon/index.rst
|
||||
@@ -74,6 +74,7 @@ Hardware Monitoring Kernel Drivers
|
||||
@@ -77,6 +77,7 @@ Hardware Monitoring Kernel Drivers
|
||||
ibmaem
|
||||
ibm-cffps
|
||||
ibmpowernv
|
||||
+ iei-wt61p803-puzzle-hwmon
|
||||
ina209
|
||||
ina2xx
|
||||
ina3221
|
||||
ina238
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ Cc: Robert Marko <robert.marko@sartura.hr>
|
|||
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -9063,6 +9063,22 @@ F: include/net/nl802154.h
|
||||
@@ -9900,6 +9900,22 @@ F: include/net/nl802154.h
|
||||
F: net/ieee802154/
|
||||
F: net/mac802154/
|
||||
|
||||
|
|
|
|||
|
|
@ -7,11 +7,11 @@
|
|||
include $(TOPDIR)/rules.mk
|
||||
|
||||
PKG_NAME:=ccache
|
||||
PKG_VERSION:=4.8.1
|
||||
PKG_VERSION:=4.8.2
|
||||
|
||||
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
|
||||
PKG_SOURCE_URL:=https://github.com/ccache/ccache/releases/download/v$(PKG_VERSION)
|
||||
PKG_HASH:=87959b6819530b3dcaeb39992f585b9fc2c7120302809741378097774919fb6f
|
||||
PKG_HASH:=3d3fb3f888a5b16c4fa7ee5214cca76348afd6130e8443de5f6f2424f2076a49
|
||||
|
||||
include $(INCLUDE_DIR)/host-build.mk
|
||||
include $(INCLUDE_DIR)/cmake.mk
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--- a/src/ccache.cpp
|
||||
+++ b/src/ccache.cpp
|
||||
@@ -1813,6 +1813,7 @@ get_manifest_key(Context& ctx, Hash& has
|
||||
@@ -1815,6 +1815,7 @@ get_manifest_key(Context& ctx, Hash& has
|
||||
"CPLUS_INCLUDE_PATH",
|
||||
"OBJC_INCLUDE_PATH",
|
||||
"OBJCPLUS_INCLUDE_PATH", // clang
|
||||
|
|
|
|||
Loading…
Reference in New Issue